Engineering Intern - Low‑Power Verification (UVM, Formal Proofs, AI)

Job Title

Engineering Intern - Low‑Power Verification (UVM, Formal Proofs, AI)

Role Summary

6‑month engineering internship within the Digital Verification team of the Secure Transactions and Identification (STI) business line in Sophia‑Antipolis. The intern will improve digital verification of Power Management for NFC SoCs through functional verification, formal proof, and exploration of AI/ML techniques for analog/mixed‑signal verification.

Experience Level

Entry-level - internship. 6‑month position starting in the first quarter of 2027.

Responsibilities

The intern will contribute to verification activities across functional, formal and AI-supported investigations:

• Analyze SoC power‑management architecture (power gating, resets, clocking) and wreal models representing analog behavior.
• Study and extend SystemVerilog testbench, write and run test scenarios for power‑state transitions, low‑power sequences and ordering.
• Implement SystemVerilog assertions (SVA) and analyze simulation results, waveform traces and coverage metrics.
• Use Jasper Formal Proof to write and verify formal properties for power controller FSMs, safety conditions, reset/isolation sequencing and deadlock checks.
• Investigate how AI/ML tools can assist analog or mixed‑signal verification workflows.
• Document results, refine constraints for formal convergence and collaborate with the verification team; potential continuation into SoC verification or IP formal proof.

Requirements

Must-have technical skills, practical abilities and personal qualities:

• Practical knowledge of digital design and verification concepts.
• Experience with SystemVerilog testbenches and writing test scenarios.
• Ability to write and use assertions (SVA) and to interpret coverage and simulation results.
• Familiarity with power‑management concepts: power‑gating, resets, clock domain interactions and waveform analysis.
• Good written and spoken English; able to work independently and investigate technical problems.

Nice-to-have:

• Experience or exposure to formal verification tools (Jasper Formal or similar).
• Familiarity with UVM testbench methodology and wreal models for analog behavior.
• Interest or prior experience in applying AI/ML to verification tasks.
• Previous exposure to SoC or IP verification flows.

Education Requirements

Bac+5 (final year engineering degree / Master level) in Integrated Circuits, Integrated Electronic Systems, Electronics, Micro‑Electronics, Embedded Systems or a closely related field. Specific engineering school degree preferred (final‑year student status expected).

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.