Engineer - Staff
QualcommJob Title
Engineer - Staff
Role Summary
Staff-level physical design engineer on the ASICs Engineering team within Qualcomm's Engineering Group. Responsible for synthesis-to-place-and-route (PnR) flows and delivering power, performance, and area (PPA) targets on advanced process nodes.
Experience Level
Senior — typically 5–10 years of hands-on experience in synthesis, PnR, physical design, and timing/power signoff. Minimum experience requirements vary by degree (see Education Requirements).
Responsibilities
Primary responsibilities include:
- Drive end-to-end PPA optimization across synthesis and PnR; collaborate across the synthesis-to-PnR boundary rather than treating it as a handoff.
- Perform floorplanning, placement, clock tree synthesis, routing, and physical implementation for advanced nodes.
- Develop and tune timing constraints and lead static timing analysis (STA) and timing closure for multi-clock, multi-corner, multi-mode (MCMM) designs.
- Implement and verify low-power design techniques (UPF, power gating, multi-voltage domains, level shifters/isolation).
- Execute aggressive area recovery, leakage/dynamic power reduction, and performance (Fmax) improvements while balancing trade-offs.
- Automate flows, write scripts, and use tooling to improve QoR and productivity; interact with architecture, verification, and senior leadership as needed.
Requirements
Must-have technical skills and experience:
- Hands-on experience with synthesis and PnR flows, QoR optimization, floorplanning, placement, CTS, routing, and equivalence checking.
- Experience on advanced process nodes with knowledge of multi/double patterning, pin access, cell legalization, and advanced DRC rules.
- Strong timing and signoff expertise, including STA (PrimeTime/Tempus) and timing closure for MCMM designs.
- Proficiency with PnR tools (Innovus/ICC2) and synthesis tools (Fusion Compiler/Genus); familiarity with LEC and low-power signoff tools.
- Proficiency in Python and Tcl; familiarity with software engineering practices such as version control and configuration management.
- Experience with power-optimization techniques: clock gating, cell sizing, Vt swapping, buffer/inverter insertion and optimization.
- Nice-to-have: experience with computer architecture and high-speed, low-power processor design; prior use of AI tools in flows.
Education Requirements
Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or a related field with 3+ years of relevant experience; OR PhD in Science, Engineering, or a related field with 2+ years of relevant experience. Preferred fields: Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
