Engineer, Scribe Layout Design

Job Title

Engineer, Scribe Layout Design

Role Summary

Design, layout and verify CMOS test structures (scribe/non-array) used for device development, modeling, reliability and fab process monitoring. The role is part of the Scribe Design Non-Array (SDNA) team and works with engineering teams in India, Japan and the US to deliver floorplanning, layout, DRC/LVS verification and in-house verification automation across Micron technology nodes.

Work includes supporting tape-outs, interfacing with customers and partner groups, and using metrics to drive improvements in design accuracy and repeatability.

Experience Level

Mid-level. Experience guidance: ME/M.Tech with at least 4 years relevant experience, or BE/B.Tech with at least 6 years relevant experience.

Responsibilities

Key responsibilities and deliverables for the Scribe Layout Design role.

• Translate technology and test requirements into CMOS test-structure (TEG) layout and floorplanning for N, N+1 and N+2 nodes.
• Perform layout verification using DRC, LVS, E-simulation and in-house verification tools; ensure design integrity.
• Run and analyze pre- and post-silicon simulations to validate designs against silicon data.
• Coordinate scribe scheduling, design changes, and tape-out activities with cross-functional teams.
• Apply and extend Micron layout methodology, simulations and automation for TEG solutions.
• Use metrics and data to improve structure accuracy, repeatability and fab performance.
• Provide technical guidance on complex, multi-disciplinary projects and advise management on critical TEG design issues.
• Maintain strong customer and partner relationships to ensure high satisfaction and timely delivery.

Requirements

Must-have technical skills and experience; followed by desirable skills.

• Must-have: Hands-on experience with EDA tools (Cadence Virtuoso layout and schematic, Calibre) and layout/verification workflows (DRC, LVS).
• Must-have: Ability to perform pre- and post-simulation and analyze results (Hspice/Finesim) with silicon correlation.
• Must-have: Strong knowledge of semiconductor device physics, parametric testing and DFM practices; understanding of Micron memory process flows.
• Must-have: Demonstrated project management skills and ability to lead complex design activities.
• Nice-to-have: Familiarity with fab process steps and device characterization.
• Nice-to-have: Experience with Linux/Unix and scripting (Python, Skill) and automation for layout and verification tasks.
• Nice-to-have: Proven problem-solving, cross-functional collaboration and strong oral and written communication skills.

Education Requirements

BE/B.Tech with at least 6 years of relevant experience; or ME/M.Tech in Electrical or Electronics Engineering (or similar discipline) with at least 4 years of relevant experience. (Degrees and years of experience explicitly required by the posting.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.