Engineer, Physical Design

Job Title

Engineer, Physical Design

Role Summary

Responsible for executing the full physical design flow (RTL → GDSII & STA) for blocks and full-chip designs, driving timing closure and tapeout activities. Works with RTL, mixed-signal/custom teams, foundries and IP vendors to integrate analog macros and achieve signoff on advanced process nodes.

Experience Level

Mid-level — requires a minimum of 2+ years of experience in physical design and timing closure.

Responsibilities

Primary responsibilities include:

• Lead block-level and full-chip place & route and timing closure (synthesis, P&R, STA, and physical verification).
• Collaborate with mixed-signal/custom design teams on floorplan and analog macro integration.
• Perform physical verification (DRC, LVS, antenna, IR/EM) and implement fixes.
• Run timing analysis, debug violations, and implement functional and timing ECOs; perform formal verification where required.
• Work on multi-mode/multi-corner timing closure, RC extraction, crosstalk analysis, and signoff flows.
• Interface with RTL designers to define constraints, clocking, and resolve integration issues.
• Set up scan insertion and integrate DFT flows.
• Develop and maintain scripts and custom flows (Tcl, Perl, C-shell) to automate and customize synthesis, P&R, and STA for FinFET technologies.

Requirements

Must-have:

• Minimum 2+ years hands-on experience in physical design and timing closure.
• Ownership of physical design and at least one taped-out project; experience with first-generation projects is required.
• Proven experience with PD flows, physical verification, and multiple tapeouts.
• Experience with synthesis, timing analysis/closure and generating ECOs.
• Familiarity with Cadence (synthesis, P&R, timing analysis and verification) or equivalent EDA toolsets.
• Strong scripting skills (Tcl, Perl, csh) and ability to create/automate methodologies and flows.
• Experience working with foundries and IP vendors on tech files, libraries, and IP collateral.
• Knowledge of timing libraries, corners/modes, process variation, and signal-integrity issues in advanced nodes (28nm and below).
• Good communication skills and ability to work in a cross-functional team under changing requirements.

Nice-to-have:

• Experience with mixed-signal integration and formal verification flows.
• Previous exposure to multiple FinFET process nodes and signoff flows.

Education Requirements

B.Tech or M.Tech in Electronics or Electrical Engineering as specified in the posting. The source does not include explicit equivalent-experience language or alternative degree/certification options.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.