Engineer I

Job Title

Engineer I

Role Summary

Join the Hardware Engineering (DV) team to verify CPU pipelines and memory subsystems, with a primary focus on the Memory Management Unit (MMU). The role emphasizes verification of TLBs, page table walkers, and memory protection mechanisms.

This is an early-career engineering role focused on developing verification tests, analyzing coverage, and collaborating with design and architecture teams to ensure microarchitectural correctness.

Experience Level

Entry-level (early-career). The posting requests approximately 2+ years of related experience.

Responsibilities

Key responsibilities include block- and subsystem-level verification of MMU components and related verification activities.

• Design, write, execute, and debug directed and random verification tests for the MMU, TLBs, and page table walkers.
• Analyze functional and code coverage to identify verification gaps and develop cover groups and assertions to close them.
• Investigate and root-cause hardware and microarchitectural issues; validate design fixes.
• Collaborate with architects and RTL designers to understand specifications and verify implementation correctness.
• Automate test flows and debugging tasks using scripting tools.

Requirements

Must-have skills and experience; preferred items listed separately.

Must-have

• 2+ years of relevant verification or hardware engineering experience.
• Strong foundation in CPU/core architecture: pipelines, caches, virtual memory, and paging mechanisms.
• Practical Verilog knowledge for RTL understanding and verification interactions.
• Basic scripting experience for automation and debugging (Python, Perl, or Bash).
• Strong analytical, problem-solving, and debugging skills; effective written and verbal communication in a team setting.
• Right to work in India and ability to pass background and reference checks; may require export-control authorizations.

Nice-to-have

• Prior internship or academic project experience in CPU or ASIC design verification.
• Familiarity with the RISC-V ISA and privileged architecture specifications.
• Assembly-level programming knowledge or C/C++ experience in embedded environments.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.