Engineer, Design Verification
The Design Verification Engineer will verify semiconductor IP and SoC blocks for data-center and accelerated infrastructure products. The role is part of the Data Centre Engineering Group and focuses on developing verification environments and testbenches to ensure performance, power and reliability targets are met.
Work closely with RTL designers, architects and system teams to plan and execute verification strategies and achieve sign-off criteria.
Mid-level — typically 3+ to 7 years of relevant verification experience. (Posting specifies Bachelor’s +5 years or Master’s +3 years.)
Primary responsibilities include implementing verification plans, creating testbenches, running regressions and debugging failures.
Must-have technical skills and experience.
Bachelor’s degree in Computer Science or Electrical Engineering with 5+ years of relevant experience, or Master’s degree in Computer Science or Electrical Engineering with 3+ years of relevant experience.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
