Engineer, Design - Digital Implementation / Auto Place & Route

Job Title

Engineer, Design - Digital Implementation / Auto Place & Route

Role Summary

Perform RTL-to-GDSII physical implementation for digital blocks and subsystems in advanced NAND Flash designs. Work within the Non-Volatile NAND Design Engineering group to meet performance, power, area, reliability, and schedule targets across technology nodes.

Experience Level

Senior-level role. The posting targets experienced engineers with demonstrated RTL-to-GDSII implementation and sign-off experience.

Responsibilities

Primary responsibilities include ownership of physical implementation flows, collaboration across multi-functional teams, and development of automation and methodologies to improve quality and cycle time.

• Own end-to-end RTL-to-GDSII physical implementation for complex digital blocks and subsystems using automated place-and-route flows.
• Develop and optimize floorplans, power distribution networks, placement, clock tree synthesis, routing, and post-route optimization strategies.
• Drive timing closure across multi-mode, multi-corner scenarios via constraint development, static timing analysis, and ECO implementation.
• Perform and resolve physical sign-off checks: DRC, LVS, antenna, signal integrity, congestion, IR-drop, electromigration, and power analysis.
• Collaborate with RTL, DFT, analog, custom layout, CAD, package, and verification teams to ensure robust integration and tape-out readiness.
• Develop scripts, metrics, and reusable methodologies to automate implementation flows and improve quality of results.
• Apply AI-assisted tools and data-driven methods to accelerate debugging, automate repetitive tasks, analyze timing/congestion/power datasets, and improve flow predictability.

Requirements

Must-have skills and experience for effective performance in this role.

• Hands-on experience with digital physical design and automated place-and-route flows for complex ASIC, SoC, or memory designs.
• Proficiency with industry-standard implementation and sign-off tools (examples: Cadence Innovus/Tempus or Synopsys Fusion Compiler/IC Compiler II/PrimeTime).
• Strong understanding of floorplanning, clock distribution, timing closure, low-power design, signal integrity, and physical verification.
• Experience with scripting and flow automation using Tcl, Python, Perl, or equivalent languages.
• Proven problem-solving, documentation, and communication skills; ability to work in global multi-functional teams.

Nice-to-have:

• Experience with NAND Flash, other non-volatile memories, or large mixed-signal SoCs and integration of digital blocks with custom/analog macros.
• Experience with advanced technology nodes, hierarchical implementation, ECO flows, and tape-out/sign-off closure.

Education Requirements

M.S. or Ph.D. in Electrical Engineering, Electronics, Computer Engineering, or a related field (explicitly listed in the posting). No alternative-equivalent-education language was provided.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.