Engineer - DEG Layout

Job Title

Engineer - DEG Layout

Role Summary

Layout Design engineer on the DPG-IPDEV team responsible for developing analog and mixed-signal IP and supporting full-chip integration for DRAM and high-bandwidth memory applications.

The role involves block-level layout development, physical verification, and cross-site collaboration to meet project schedules for high-performance and AI-targeted systems.

Experience Level

Mid-level — typically 3 to 7 years of relevant analog/custom layout experience in advanced CMOS processes.

Responsibilities

Primary responsibilities include creating and delivering high-quality layouts and supporting verification and integration.

• Design and develop critical analog, mixed-signal, custom digital blocks, and support full-chip integration.
• Perform physical verification tasks (LVS/DRC/Antenna), quality checks, and prepare support documentation.
• Deliver block-level layouts on schedule with required quality metrics.
• Estimate area/time, plan work, schedule tasks, and execute across multiple concurrent projects.
• Coordinate and communicate with global engineering teams to ensure successful layout handoffs and tape-outs.
• Contribute to project management and support multiple tape-out cycles as needed.

Requirements

Must-have technical skills and experience; concise list of job-critical qualifications.

• 3 to 7 years of analog/custom layout design experience in advanced CMOS processes (Planar, FinFET).
• Proficiency with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS (required).
• Hands-on experience creating layouts for blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps, current mirrors, comparators, and differential amplifiers.
• Strong understanding of analog layout fundamentals: matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and device parasitics.
• Ability to assess layout effects on speed, capacitance, power, and area; implement design constraints and hierarchy for memory architectures.
• Problem-solving skills in physical verification of custom layouts and readiness to support tape-outs.
• Excellent verbal and written communication skills for global teamwork.

Nice-to-have:

• Experience supporting multiple tape-outs and exploring AI-related tools in daily tasks.

Education Requirements

BE or MTech in Electronics or VLSI Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.