Engineer 1
The Engineer I will join the Hardware Engineering (DV) team to verify CPU pipelines and memory subsystems with a focus on the Memory Management Unit (MMU). The role involves block- and subsystem-level verification, writing tests, and working with design and architecture teams to validate fixes.
This is an early-career engineering position aimed at building expertise in CPU verification and RISC-V architecture.
Entry-level / Early-career. The posting requests approximately 1+ years of experience; suitable for recent graduates or engineers with early professional experience.
Primary responsibilities include verification of MMU components, test development, coverage analysis, and cross-team collaboration.
Must-have technical skills and experience; preferred items listed separately.
Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, Computer Science, or a related technical field.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
