Emulation Engineer

Job Title

Emulation Engineer

Role Summary

Senior/Staff emulation engineer on the Emulation team responsible for building emulation infrastructure, flows, and debug methodology for advanced connectivity SoCs. The role focuses on delivering performant, functionally accurate silicon verification across emulation, SoC simulation, firmware/software bring-up, and post-silicon validation.

Experience Level

Senior / Staff-level role. The posting targets experienced candidates; explicit years of experience are not specified.

Responsibilities

Primary responsibilities include strategy, bring-up, integration, automation, and cross-team collaboration for large-scale emulation of connectivity SoCs.

• Define and execute emulation strategy and test plans for complex connectivity SoCs.
• Bring up and debug large-scale models on commercial emulation platforms (e.g. Cadence Palladium, Zebu, Veloce).
• Integrate adapters, accelerated VIP, and memory models for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and (Q)SPI; develop custom transactors when needed.
• Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and tests.
• Create reusable transactors, agents, stubs, bridges, checkers, and acceleration flows.
• Improve emulation performance and resource utilization: compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and trace management.
• Build automation for regression triage, debug, model usability, and engineering productivity.
• Develop practical LLM-based tooling for log analysis, waveform triage, debug assistance, and flow generation.
• Collaborate with architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams.

Requirements

Must-have technical skills and capabilities required to perform the role, followed by optional skills that strengthen a candidate's fit.

• Must have: Hands-on experience with SoC emulation or system-level validation.
• Experience with at least one commercial emulation platform (e.g. Palladium, Zebu, Veloce).
• Working Verilog/SystemVerilog and waveform-debug skills sufficient to develop custom transactors or agents.
• Strong software and automation skills: Python plus one or more of C, C++, Rust, Tcl, or shell scripting.
• Proven ability to build tools and infrastructure (not just run existing flows).
• Strong system-level debug instincts across RTL, firmware, and software; ability to work independently and across teams.

Nice-to-have:

• UVM or hybrid SoC testbench development experience.
• Experience integrating cycle-accurate, software, or reference models into emulation/DV flows.
• Rust in verification/emulation workflows or strong interest in adopting it.
• Familiarity with Bazel or large-scale build/regression systems.
• Reusable stimulus across simulation, emulation, and post-silicon.
• Experience applying AI/LLMs to build engineering tools (debug, triage, flow generation).
• Domain experience with connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics.
• Firmware or driver bring-up experience on emulation platforms and experience scaling emulation infrastructure across projects.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.