EMIB-T Substrate Yield Lead

Job Title

EMIB-T Substrate Yield Lead

Role Summary

Lead end-to-end substrate yield performance for EMIB-T advanced packaging technology, driving yield improvements from identification through execution to enable technology development and manufacturing readiness for multiple product groups.

This role works across substrate suppliers, packaging and manufacturing teams, design, quality & reliability, and platform integration to close critical yield and supplier issues and scale EMIB-T into production.

Experience Level

Mid-level. Role expects significant hands-on experience in semiconductor manufacturing and yield engineering; typically 5+ years of relevant industry experience.

Responsibilities

Primary responsibilities include owning yield performance and coordinating cross-functional execution.

• Own end-to-end substrate yield for EMIB-T technology development and manufacturing readiness.
• Drive DFM/DFY engagement, defect pareto closure, process optimization, and yield improvement plans from signal identification through execution.
• Lead daily yield huddles and cross-functional reviews to track execution and address yield risks promptly.
• Identify, prioritize, and close critical yield, reliability, process, and supplier issues with minimal oversight.
• Partner with substrate suppliers, module engineers, integration, manufacturing, design, and Q&R organizations to meet milestones.
• Establish accountability, track actions, remove roadblocks, and ensure on-schedule delivery of commitments.
• Drive yield readiness assessments, risk mitigation plans, and prepare executive-level communications for program reviews.
• Define and scale yield intelligence infrastructure: dashboards, automated analytics, computer vision, AI/ML defect detection, and automated defect classification.
• Enable deployment and scaling of EMIB-T across multiple products and business groups.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5+ years experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, or process engineering.
• Hands-on experience in substrate or advanced packaging yield engineering: statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution.
• Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, or AI/ML-based defect detection and classification.
• Strong analytical and problem-solving skills; ability to make data-driven decisions under ambiguity.
• Proven ability to work across organizations, influence stakeholders, and manage complex technical issues to closure.
• Demonstrated urgency in execution and capability to run high-visibility program activities.

Nice-to-have:

• Experience working directly with substrate suppliers and external manufacturing partners.
• Program leadership experience coordinating cross-functional technical teams.
• Experience with advanced packaging technologies such as EMIB, EMIB-T, TSV, 2.5D/3D integration, substrates, or heterogeneous integration.
• Prior experience supporting technology development, qualification, and manufacturing ramp.

Education Requirements

Master's degree with 6+ years of experience, or PhD with 4+ years, in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline (as stated in the posting).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.