Elite FPGA Engineer — DSP/Verilog (Equity)

Job Title

Elite FPGA Engineer — DSP/Verilog (Equity)

Role Summary

Join a Los Angeles-based technology scale-up to own system algorithms and FPGA implementations for math- and data-intensive products. You will work closely with a small engineering team to design, implement, and validate FPGA systems used in production hardware.

Experience Level

Entry-level / Early-career — the role expects approximately 2+ years of relevant FPGA development experience.

Responsibilities

Primary responsibilities include system-level algorithm ownership, FPGA design, and cross-functional integration.

• Design and implement DSP and data-processing algorithms on FPGA using Verilog/SystemVerilog.
• Develop and maintain RTL, testbenches, and simulation flows.
• Perform synthesis, timing closure, and resource optimization for target FPGA platforms.
• Integrate FPGA firmware with software, hardware, and verification teams.
• Debug hardware/software interactions and support bring-up and validation on physical boards.
• Document designs, trade-offs, and verification results for engineering reviews.

Requirements

Must-have technical skills and experience; listed concise and separated from preferred items.

• Must-have: Minimum ~2 years building FPGA systems with practical Verilog/SystemVerilog experience.
• Must-have: Strong background in DSP, numerical methods, or algorithm development for data processing.
• Must-have: Experience with FPGA toolflows (synthesis, simulation, timing analysis) and board bring-up.
• Nice-to-have: Experience with Xilinx or Intel FPGA toolchains, high-speed interfaces, and hardware/software integration.
• Nice-to-have: Familiarity with scripting for automation and verification (Python, TCL) and experience with testbench development.

Education Requirements

Not specified.

About the Company

Company: Beacon Industries

Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.