Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer

Job Title

Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer

Role Summary

Technical lead responsible for end-to-end tape-out flow for electronic-photonics integrated circuits on a 300 mm graphene photonics platform. The role owns GDS database integration, mask data preparation, formal mask release, and post-tapeout support while coordinating across design, fabrication, test, and packaging teams.

Experience Level

Mid-level — requires professional experience; the posting specifies 5+ years of experience in semiconductor or photonics tape-out, layout integration, and Mask Data Preparation (MDP).

Responsibilities

Primary deliverables and day-to-day responsibilities:

• Own complete tape-out flow: mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign-off, and rule file maintenance for PIC–EIC integration and new nodes.
• Lead GDS and reticle-to-fab delivery and formal mask release; ensure layers, formats, and data structures meet foundry/mask-shop specifications.
• Drive DFM/DFT integration for yield optimization, hotspot mitigation, layout optimization, scan chains, test pads, and optical probe structures.
• Design and integrate special GDS structures (kerf, seal ring, frame, scanner marks, metrology/PCM structures, ESD layouts, and RDL packaging interfaces).
• Act as primary interface with mask shops, foundry lithography/metrology teams, EDA vendors, and cross-functional analog, digital, packaging, and reliability teams.
• Maintain GDS version control and audit-trail archiving; support first-silicon debug and layout-based failure analysis.
• Improve and maintain MDP job decks, jobdeck views, and mask-data best practices across projects.

Requirements

Must-have technical skills and experience. Nice-to-have items listed separately.

• 5+ years of practical experience in semiconductor or photonics tape-out, layout integration, and Mask Data Preparation (MDP).
• Proven experience with GDSII and OASIS data formats and tape-out data flows.
• Hands-on with DRC/LVS/ERC verification flows and industry tools such as Calibre and Synopsys ICV; experience authoring MDP job decks and JDV.
• Practical knowledge of production tape-out requirements: DFM, DFT, ESD, seal ring/kerf, and RDL layout implementation.
• Familiarity with OPC flows and coordinating OPC/metrology with mask shops and foundry partners.
• Strong cross-team communication and vendor coordination skills (mask shops, foundries, EDA vendors).

Nice-to-have:

• Experience with Photonic IC technologies (Si, SiN), RF photonics, or photonic/electronic co-design EDA tools (e.g., Cadence EPIC, Lumerical).
• Experience with graphene or 2D-material integration, or prior work in mask-shop or EDA software environments (Synopsys, Siemens, Cadence, Toppan, Photronics, Compugraphics, Tekscend).

Education Requirements

MS or PhD in Electrical Engineering, Physics, or a related technical field is specified.

About the Company

Company: Black Semiconductor

Headquarters: Aachen, Germany

Black Semiconductor is revolutionizing the semiconductor industry with innovative graphene solutions that enhance chip connectivity and efficiency. By merging electronic computing and photonic communication, the company aims to reshape how chips interact, driving significant advancements in power and speed. Their human-centered approach fosters collaboration and continuous learning, making it a dynamic place for professionals to grow and make an impact.