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DV Intern

Etched
August 27, 2026
Internship
On-site
San Jose, California, United States
Verification Jobs, Level - Entry or Early Career

Job Title

DV Intern

Role Summary

As a Design Verification intern at Etched you will validate custom IP blocks (systolic arrays, DMA engines, NoCs) for correctness and performance and help make them silicon-ready. You will work closely with architects, RTL designers, and software/firmware/emulation teams across the full hardware–software stack.

12-week paid internship based in San Jose, CA. Positions open for Fall '26, Spring '27, and Summer '27. For questions: internships@etched.com

Experience Level

Entry-level — internship for current undergraduate or graduate students; suitable for those with coursework or project experience in digital logic and verification.

Responsibilities

Primary responsibilities include:

  • Design and execute verification plans for custom IP (systolic arrays, DMA engines, NoCs).
  • Develop verification environments, testbenches, and directed/stress/random tests using SystemVerilog, UVM, and scripting languages.
  • Integrate verification with software/firmware and emulation flows to validate system-level behavior and performance.
  • Debug RTL issues, analyze failing tests, and work with designers to isolate root causes.
  • Automate regression runs, collect coverage metrics, and document verification results.
  • Participate in design and code reviews and collaborate across disciplines (architecture, RTL, SW/FW, physical design).

Requirements

Must-have skills and experience:

  • Familiarity with high-speed digital logic and timing concepts.
  • Exposure to ASIC or SoC design concepts and flows.
  • Experience with SystemVerilog, UVM, or Python for verification.
  • Experience writing testbenches and performing verification tasks.
  • Familiarity with physical design flows and EDA tooling.
  • Quick learner with the ability to pick up transformer/ML model concepts relevant to verification tasks.

Nice-to-have:

  • Experience with modern ML/LLM model architectures and how they map to accelerator hardware.
  • Formal verification experience or additional verification methodology exposure.
  • Strong Python or scripting skills for automation and tooling.

Education Requirements

Progress toward a Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or a related technical field (e.g., computer science, physics, mathematics). Intern candidates are expected to be current students in these programs.


About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.

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Date Posted: 2026-08-27