DV Engineer

Job Title

DV Engineer

Role Summary

As a design verification (DV) engineer at Broadcom, you will develop and execute verification strategies for hardware IP and SoC projects, create and maintain verification environments, write and run tests, analyze simulation results, and collaborate with design and validation teams.

This posting contains minimal detail; the responsibilities and requirements listed below are concise, typical expectations for a DV role and may not reflect every detail of this specific opening.

Experience Level

Mid-level. Specific years of experience were not provided.

Responsibilities

The posting did not provide a detailed responsibilities list. Typical responsibilities for this role may include:

• Develop and maintain verification environments and testbenches (for example, SystemVerilog and UVM).
• Design and implement directed and constrained-random tests and verification plans.
• Run and analyze simulations, debug functional issues, and track defects to closure.
• Work closely with RTL designers, architects, and validation teams to resolve issues.
• Improve verification automation, regression infrastructure, and coverage closure processes.

Requirements

The posting did not list explicit requirements. Typical expectations are provided below:

• Must-have (typical): Practical experience in design verification and familiarity with SystemVerilog or equivalent verification languages.
• Nice-to-have: Experience with UVM, scripting (Python/Perl/Tcl), formal verification, emulation, or hardware bring-up.

Education Requirements

Not specified.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.