DSP Designer

Job Title

DSP Designer

Role Summary

The DSP Designer develops and delivers signal-processing algorithms from concept through simulation, fixed-point implementation, and hardware bring-up. The role interfaces directly with clients and internal FPGA/HDL and hardware teams to translate algorithms into bit-true, hardware-feasible designs.

Experience Level

Mid-level. The posting does not specify required years of experience; the role may be adjusted to fit candidates at different career stages when appropriate.

Responsibilities

Primary responsibilities include algorithm development, validation, and collaboration to enable HDL/FPGA implementation and lab bring-up.

• Develop and simulate DSP algorithms (equalization, filtering, estimation, detection) in MATLAB/Simulink and/or Python.
• Perform quantization and bit-width analysis; produce bit-true fixed-point models for HDL implementation.
• Collaborate with FPGA/HDL and hardware teams to design hardware-feasible architectures (pipelining, MAC/resource budgeting, timing considerations).
• Provide golden-model test vectors and support co-simulation for HDL verification.
• Support lab bring-up, characterization, and tuning of DSP-based hardware against real-world channel/sensor behavior.
• Adapt DSP toolkits and algorithms to new client domains, standards, and product requirements.
• Document design decisions, trade-offs, and validation results for clients and internal reference.

Requirements

Must-have technical skills and capabilities for successful performance in this role.

• Strong foundation in signals and systems (Fourier/Z-transform, digital filter design, sampling theory).
• Practical experience with estimation/detection theory or adaptive filtering (matched filtering, MMSE, Kalman, LMS/RLS).
• Proficiency in MATLAB/Simulink and/or Python for algorithm design and simulation.
• Experience with fixed-point conversion and quantization trade-off analysis.
• Proven ability to work across the algorithm-to-hardware boundary and collaborate with HDL/FPGA teams.
• Experience supporting HDL verification via test vectors and co-simulation.
• Hands-on experience with lab bring-up and tuning of DSP hardware.
• Strong verbal and written communication skills; able to explain algorithm trade-offs to non-DSP stakeholders.
• Comfortable incorporating AI/ML techniques into engineering workflows.

Nice-to-have:

• Experience in optical/wireless communications, radar/sensing, motor control, biomedical signal processing, or semiconductor test.
• Experience with high-speed SerDes and PAM4 signaling (FFE/CTLE/DFE, link training, FEC awareness).
• Familiarity with AMD Adaptive Computing products (Versal, Alveo) or embedded x86 platforms.
• Familiarity with HDL Coder, HLS, or Simulink-to-HDL workflows.
• Hands-on use of lab instruments (oscilloscope, VNA, BERT) or domain-equivalent test equipment.
• Exposure to safety-critical/regulatory development processes (DO-178C/DO-254, ISO 26262, IEC 62304/60601).
• Experience applying AI/ML to signal processing on FPGAs, GPUs, NPUs, or CPUs.
• Experience with dedicated DSP processors and RF front-end systems (ADC/DAC, DUC/DDC).

Education Requirements

BS, MS, or PhD in Electrical Engineering, Applied Physics, or a related field.

About the Company

Company: Fidus

Headquarters: Ottawa, Canada

Fidus is a global leader and dynamic high-tech design firm specializing in electronic product development. With expertise in ASIC, FPGA hardware, software, and signal integrity, Fidus delivers next-generation products for clients across diverse industries including Telecom, Aerospace, Semiconductors, and Medical. Established in 2001, Fidus has successfully completed over 4,000 projects for more than 400 customers, maintaining a strong focus on innovation and excellence in service.