DRAM PHY Designer, up to Staff

Job Title

DRAM PHY Designer, up to Staff

Role Summary

Design and deliver high-speed DRAM PHY and IO circuitry for memory-centric compute systems used in data center, mobile, compute, and XR platforms. The role works across process, package, SoC, memory controller, and architecture teams to define PHY architectures, validate signal integrity, and enable manufacturable implementations.

Experience Level

Senior (Staff). See Education Requirements for specific degree-to-experience guidance.

Responsibilities

Key responsibilities focus on circuit/IP design, simulation, and integration of memory PHY and IO subsystems.

• Architect, design, and implement high-speed PHY circuits and IO interfaces (e.g., LPDDR, HBM).
• Create and optimize layouts for placement, signal routing, and power delivery.
• Develop robust power-delivery solutions for PHY circuits and incorporate power-management features.
• Perform signal-integrity and SNR analysis with package/board s-parameter models.
• Run pre-layout and post-layout mixed-signal simulations across PVT corners.
• Develop behavioral, timing, and power models to guide architecture and system trade-offs.
• Floorplan PHY blocks considering manufacturability, testability, repairability, and performance.
• Document designs and collaborate with cross-functional teams including packaging, emulation, memory controller, and SoC teams.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Hands-on experience designing high-speed PHY circuits and analog/digital mixed-signal blocks.
• Knowledge of timing circuits such as DLLs and PLLs.
• Experience with SERDES, phase/duty-cycle adjustment, and IO circuit techniques.
• Understanding of signal integrity, eye diagrams, noise sources, and SNR analysis.
• Experience with pre-layout and post-layout mixed-mode simulation and EDA design/simulation tools.
• Layout and floorplanning experience focusing on signal routing and power delivery.
• Ability to develop behavioral, timing, and power models for system architects.
• Strong problem-solving, written/verbal communication, and ability to work independently or in teams.

Nice-to-have:

• Familiarity with package design and package/board interactions.
• Scripting experience (Perl, Python) for automation and tool flows.
• Familiarity with DRAM datasheets and IO interface specifications.
• Experience with architecture/design tools and design verification methods.
• Experience interacting with senior leadership and influencing technical decisions.

Education Requirements

Degree and equivalent-experience guidance found in the posting: Bachelor's, Master's, or PhD in Science/Engineering or related fields; specific fields include Electrical/Electronic Engineering, Computer Engineering, Computer Science, or related technical disciplines. The posting specifies common equivalencies: Bachelor's +4 years of relevant ASIC design/verification/validation/integration experience, Master's +3 years, or PhD +2 years. Preferred: Master's in Electrical/Electronic Engineering, Computer Engineering, or Computer Science and senior-level experience (example preferred: 6+ years of ASIC design experience).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.