DRAM Circuit Designer, up to Staff

Job Title

DRAM Circuit Designer (up to Staff)

Role Summary

Design and optimize custom DRAM core circuits and arrays to improve bandwidth, latency, power, thermal, and area efficiency for memory-centric compute systems. Work on circuit design, layout, timing, power delivery, and manufacturability for DRAM bank circuits, sense amplifiers, datapaths, decoders, and voltage generation.

Collaborate across process & packaging, AI/compute architects, memory controller, SoC teams, and emulation to translate architecture trade-offs into implementable circuit solutions.

Experience Level

Senior. Typical experience expectation: approximately 4+ years post-degree (Bachelor's+4 years, Master's+3 years, PhD+2 years) depending on degree and role level.

Responsibilities

Key responsibilities include:

• Design, simulate, and optimize DRAM bank circuits (decoder, sense amp, datapath, voltage generation) for margin, timing, power, and area.
• Develop timing control and circuit techniques for energy- and area-efficient cell arrays.
• Create placements and floorplans considering TSVs, power distribution, testability, and repairability.
• Architect robust high-bandwidth bus/fabric distribution across DRAM array, compute, and I/O.
• Produce layouts that balance circuit placement, routing, and power delivery constraints.
• Use EDA and simulation tools to assess circuit behavior and manufacturability readiness.
• Develop behavioral, timing, and power models to guide architectural trade-offs for AI, compute, and mobile workloads.

Requirements

Must-have and preferred skills:

• Must-have: Experience in mixed-signal circuit design, layout, and simulation; memory array and datapath design (SRAM/DRAM/Flash/ROM/OTP); high-speed design principles and reliability.
• Proficiency with industry EDA tools and scripting for simulation/analysis; familiarity with MATLAB and Python.
• Knowledge of memory architecture, buses, and advanced packaging including 2.5D/3D integration.
• Experience creating behavioral, timing, and power models to support architecture decisions.
• Good communication, problem-solving skills, and ability to work independently and in cross-functional teams.
• Nice-to-have: Verilog/Verilog-A/Verilog-AMS modeling experience; DRAM architecture performance assessment; experience with C/C++ or scripting languages (Perl/Python); familiarity with DRAM datasheets and I/O interfaces.

Education Requirements

Degrees: Bachelor's, Master's, or Ph.D. in Science, Engineering, Electrical Engineering, or a related technical field. The posting specifies degree-to-experience mappings: Bachelor's + ~4 years, Master's + ~3 years, PhD + ~2 years of relevant ASIC/design experience. Equivalent practical experience is accepted per the degree/experience combinations.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.