DPU Silicon RAS and Debug Architect

Job Title

DPU Silicon RAS and Debug Architect

Role Summary

Design the reliability, availability, serviceability (RAS) and debug/trace architecture for Meta's Data Processing Unit (DPU) ASICs. Partner with RTL, firmware, driver, design verification (DV), physical design (PD), and bring-up teams to define error-detection/correction/reporting, FIT budgeting, trace/telemetry, and the hardware–firmware–software interfaces required for post-silicon debug and production deployments.

Experience Level

Level: Senior. Requires significant domain experience; minimum 8+ years industry experience in RAS and debug/trace architectures (15+ years listed as preferred).

Responsibilities

Primary responsibilities include architecture definition, cross-team collaboration, and support through silicon bring-up.

• Own RAS and debug/trace architecture for DPUs from early path-finding through silicon bring-up.
• Set FIT-rate targets based on deployment models and budget them across memories, logic, interfaces, and links.
• Define error detection, correction, reporting, and containment mechanisms (parity, ECC/SECDED, poisoning, logging, escalation paths).
• Design on-chip trace, event/counter telemetry, crash/state capture, and debug-access models for post-silicon and firmware/software debugging.
• Specify hardware vs firmware vs software responsibilities and the register, programming, error/interrupt, and telemetry interfaces exposed to firmware and host software.
• Collaborate with design, DV, PD, and DFT teams to balance functionality with PPA and verification complexity; define features to simplify DV and integration.
• Support post-silicon bring-up and resolve interface and integration issues with cross-functional teams.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 8+ years of relevant industry experience architecting RAS and debug/trace architectures and hardware/software interfaces for NIC/DPU or comparable ASICs.
• Proven ability to perform FIT-rate estimation and reliability budgeting across complex designs.
• Deep knowledge of error-protection mechanisms (parity, ECC/SECDED, CRC, poisoning, redundancy) and trade-offs in area, latency, and power.
• Experience with memory and interface RAS: LPDDR/DDR RAS (on-die ECC, scrubbing, post-package repair) and PCIe RAS (AER, ECRC, link recovery).
• Experience with error reporting and handling architectures (ARM and/or x86): logging, registers, interrupts, machine-check/AER-style reporting and firmware escalation.
• Experience with on-chip debug and trace architectures (JTAG/debug access, trace, break/watchpoints, crash/state capture).
• Familiarity with performance-monitoring architectures (hardware counters, event telemetry) and their use in post-silicon debug.
• Familiarity with DFT concepts (scan, MBIST/LBIST, boundary scan) and processor ISA debug/trace mechanisms (e.g., ETM).
• Knowledge of relevant industry standards and specifications (e.g., OCP server/RAS/telemetry, JEDEC, PCIe).
• Proven ability to drive analysis independently and influence architectural direction using data.
• Preferred: experience with HDLs (SystemVerilog, VHDL) and creating automation for debug/telemetry collection and analysis (e.g., Python scripting).
• Preferred: experience defining FIT budgets, soft-error rate (SER) analysis, functional-safety familiarity, and designing machine-check/AER-style firmware flows and post-silicon tooling.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a relevant technical field, or equivalent practical experience. PhD in CS, CE, or EE is listed as preferred.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.