DPU RAS and Debug Architect, Infrastructure Silicon

Job Title

DPU RAS and Debug Architect, Infrastructure Silicon

Role Summary

Define the reliability, availability, serviceability (RAS), trace/debug, and telemetry architecture for Data Processing Unit (DPU) ASICs used in Meta's data centers. The role spans early path‑finding through RTL implementation and post‑silicon bring‑up, and requires close collaboration with firmware, driver, DV, design, and platform teams.

Work includes FIT-rate budgeting, error detection/correction/reporting, on‑chip trace and telemetry, and decisions about hardware vs firmware vs software responsibilities.

Experience Level

Senior - requires significant industry experience; the posting specifies 8+ years of relevant experience architecting RAS and debug/trace architectures for NICs/DPUs or comparable ASICs.

Responsibilities

Primary responsibilities from architecture definition through silicon bring‑up:

• Own RAS and debug architecture for DPUs: error detection, correction, reporting, FIT budgeting, trace, and telemetry.
• Set FIT‑rate targets from deployment models and allocate budgets across memories, logic, interfaces, and links.
• Define error detection/correction/containment approaches (parity, ECC/SECDED, poisoning, logging) and how errors surface to firmware, host software, and platform management.
• Design trace, debug, and performance‑monitoring infrastructure for post‑silicon and software/firmware debug (on‑chip trace, counters, crash/state capture, debug access model).
• Specify register/programming models, interrupt/error models, and hardware/firmware/software interfaces.
• Collaborate with design, DV, PD, DFT, and firmware teams to balance features, PPA, and testability; support integration and post‑silicon bring‑up.

Requirements

Must-have technical experience and capabilities:

• Proven experience architecting RAS and debug/trace architectures and their hardware/software interfaces for NIC/DPU or comparable ASICs.
• Practical knowledge of RAS concepts: FIT estimation/budgeting, failure modes including silent data corruption, error detection, correction, containment, and data center reliability requirements.
• Experience with error‑protection mechanisms (parity, ECC/SECDED, CRC, data poisoning, redundancy) and trade‑offs in area, latency, and power.
• Memory and interface RAS experience (LPDDR/DDR ECC/on‑die ECC/scrubbing/post‑package repair; PCIe RAS including AER and ECRC).
• Error reporting and handling architectures (error logging, registers, interrupts, machine‑check/AER reporting) and escalation to firmware/host/BMC.
• On‑chip debug and trace architecture experience (JTAG/debug access, on‑chip trace, breakpoints/watchpoints, crash/state capture).
• Performance‑monitoring architectures (hardware counters, event telemetry) used for post‑silicon and firmware/software debug.
• DFT familiarity (scan, MBIST/LBIST, boundary scan) and interaction with RAS/debug.
• Familiarity with relevant industry standards (e.g., JEDEC, PCIe, OCP) and the ability to drive analysis and influence architecture decisions with data.

Nice-to-have:

• Experience with hardware description languages and ASIC simulation flows.
• Experience designing on‑chip trace subsystems and associated post‑silicon debug tooling.
• Experience defining FIT budgets for hyperscale silicon, functional‑safety familiarity, and automation/scripting for debug and telemetry data collection.

Education Requirements

Required: Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Preferred: PhD in Computer Science, Computer Engineering, or Electrical Engineering. Equivalent practical experience is explicitly accepted.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.