DPU Power Architect, Infrastructure Silicon

Job Title

DPU Power Architect, Infrastructure Silicon

Role Summary

Drive power modeling, analysis, and architectural power optimization for Meta's Data Processing Unit (DPU) and SmartNIC/IPU designs. Work across architecture, RTL/gate-level analysis, and post-silicon correlation to improve performance-per-watt on real data center workloads.

Experience Level

Senior level. The posting lists preferred experience of 15+ years; equivalent practical experience is acceptable.

Responsibilities

Key responsibilities include workload-driven power analysis and architectural optimization.

• Analyze real-world DPU software use cases (network virtualization, storage offload, crypto/compression, packet processing) to identify power bottlenecks.
• Build and maintain workload-driven, system-level power models and power rollups from early estimates through RTL and gate-level analysis.
• Quantify architectural and micro-architectural trade-offs (energy-per-transaction, power-per-bit, performance-per-watt) to guide design decisions.
• Define and drive architecture features for power savings (DVFS, AVS, power gating, clock gating, activity throttling, power state management, workload-aware policies).
• Analyze SoC pipelines and data movement (host-to-DPU, memory/fabric/network) to optimize power vs. performance.
• Own power budgets and provide power-delivery and thermal inputs with cross-functional teams (design, physical design, firmware, platform, software).
• Correlate pre-silicon power projections with post-silicon measurements and improve methodologies based on findings.

Requirements

Must-have technical skills and experience; followed by concise nice-to-have items.

Must-have:

• Experience in workload analysis and abstracting power-relevant behaviors into models for architectural analysis.
• Experience building system-level power models and tracking them from early estimates through RTL/gate-level power analysis.
• Experience defining or evaluating architectural power-saving features such as DVFS, power gating, and clock gating.
• Understanding of SoC pipelines and how data movement impacts power versus performance.
• Proficiency in model development and automation languages (e.g., Python, C/C++, SystemC).
• Proven ability to drive analysis independently and influence architectural direction through data.

Nice-to-have:

• Power management firmware/software co-design, on-die telemetry, or closed-loop power/thermal control experience.
• Experience with simulation/emulation for ASIC flows and long-window activity capture (FSDB/SAIF).
• Experience with low-power implementation flows (multi-voltage/UPF, retention/isolation strategies).
• Experience building power modeling and regression infrastructure for hyperscale data center ASICs.
• Familiarity with post-silicon power measurement, telemetry, and model-to-hardware correlation.
• Experience with industry-standard power estimation and sign-off tools (e.g., Synopsys PrimePower/PTPX, Cadence Joules, Ansys PowerArtist).
• Familiarity with power delivery network, voltage droop/di-dt analysis, and rack/platform-level power/thermal constraints.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Preferred: PhD in Computer Science, Computer Engineering, or Electrical Engineering.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.