DPU Performance Architect, Infrastructure Silicon

Job Title

DPU Performance Architect, Infrastructure Silicon

Role Summary

Drive performance modeling, analysis, and validation of Data Processing Unit (DPU) architectures for data-center infrastructure silicon (SmartNICs/IPUs/DPUs). Influence architecture and microarchitecture decisions from early path‑finding through RTL validation and silicon correlation.

Work within the Infrastructure Silicon team to quantify trade-offs, develop representative models and benchmarks, and correlate pre‑silicon projections with post‑silicon measurements.

Experience Level

Senior-level - requires 8+ years of relevant industry experience with independent analysis and the ability to influence architectural direction.

Responsibilities

Technical responsibilities include modeling, analysis, validation, and correlation across pre‑ and post‑silicon stages.

• Analyze end-to-end performance of current and future SmartNIC/IPU/DPU architectures, including host-to-DPU offload options and SoC architectural alternatives.
• Quantify architectural and microarchitectural trade-offs (performance, power, area) to inform design decisions.
• Characterize DPU workloads and abstract performance-relevant behaviors into representative models and synthetic benchmarks.
• Develop and enhance performance models, simulation tools, and evaluation methodologies for future DPU architectures.
• Drive RTL performance validation: create performance test plans, define coverage criteria, execute validation, and correlate RTL results against architectural models.
• Correlate pre-silicon performance projections with post-silicon measurements and improve methodologies based on findings.

Requirements

Required skills and experience to perform the role, followed by additional desirable competencies.

Must-have

• 8+ years of industry experience in analytical/tool-based modeling and performance analysis focused on networking and storage architectures.
• Deep understanding of DPU architectures: network virtualization, storage disaggregation, and networking/storage protocols such as RoCE and NVMe.
• Experience in workload analysis and characterizing performance-relevant behaviors for modeling and benchmarking.
• Proficiency in model development languages (e.g., Python, C/C++, SystemC).
• Familiarity with data-center workloads and benchmarking methodologies.
• Experience with RTL performance validation, authoring and executing performance test plans, and correlating models with hardware measurements.
• Ability to drive analysis independently and influence architectural direction using data.

Nice-to-have

• 15+ years of relevant industry experience.
• Experience with hardware description languages (SystemVerilog, VHDL) and ASIC simulation environments.
• Experience building or scaling performance-modeling infrastructure for hyperscale data-center ASICs.
• Experience developing Python-based automation for simulation orchestration, regression testing, and performance data analysis.
• Experience with GPU/ML workloads, multi-threaded programming paradigms, high-level synthesis, or PPA-driven microarchitectural optimization.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a relevant technical field, or equivalent practical experience. PhD in Computer Science, Computer Engineering, or Electrical Engineering is listed as preferred.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.