DPU Networking Architect, Infrastructure Silicon

Job Title

DPU Networking Architect, Infrastructure Silicon

Role Summary

Design and own the networking datapath for Meta's Data Processing Units (DPUs), including packet processing, offloads, network virtualization, RDMA/storage transports, and inline security. Lead decisions on which functions belong in hardware, firmware, or host software and carry those decisions from early exploration through silicon bring-up.

Collaborate closely with firmware, driver, RTL, design verification, and physical design teams; back architecture choices with performance and PPA analysis and support post-silicon validation and integration.

Experience Level

Senior - typically requires 8+ years of relevant industry experience architecting networking datapaths and packet-processing pipelines for NICs/DPUs or comparable ASICs.

Responsibilities

Own architecture and interfaces for the DPU networking datapath and drive implementation trade-offs across hardware, firmware, and host software.

• Architect packet-processing/datapath engines, offloads, network virtualization/overlays, RDMA/storage transports, and inline security for DPUs.
• Decide placement of features across datapath engines, firmware, and host software and define clean interfaces between them.
• Define programming and control models: match-action tables, rule/flow programming, register/descriptor interfaces, and offload APIs for firmware and drivers.
• Collaborate with firmware, driver, software, RTL, DV, and PD teams to ensure usable, efficient, and verifiable datapath interfaces and features.
• Perform PPA and performance trade-off analysis and partner with modeling teams when deeper study is required.
• Support design, verification, and physical-design teams to resolve integration issues and assist with post-silicon networking bring-up and validation.

Requirements

Must-have:

• 8+ years of industry experience architecting networking datapaths and packet-processing pipelines and their hardware/software interfaces for NICs, DPUs, SmartNICs, or comparable ASICs.
• Experience with SmartNIC/IPU/DPU architectures and typical usages: network virtualization, storage disaggregation, overlay networking, virtual switch, firewall/ACLs, and gateway offloads.
• Working knowledge of datacenter networking technologies and offload mechanisms (Ethernet, IPv6, TCP/UDP, Geneve, PSP, SRv6; TCP segmentation/reassembly, checksum, receive-side scaling).
• Experience with RDMA and storage protocols and fabrics such as RoCEv2 and NVMe/NVMe-over-Fabric.
• Familiarity with congestion control (e.g., DCQCN) and emerging transports (e.g., UET) and their performance implications.
• Experience with on-chip scheduling, arbitration, and QoS mechanisms and their impact on latency, fairness, and throughput.
• Understanding of datacenter fabric architectures and topologies (Clos/fat-tree, rails, ECMP/load balancing) and end-to-end latency/congestion behavior.
• Knowledge of cryptography concepts and inline data encryption techniques relevant to networking datapaths.
• Experience with domain-specific dataplane languages (e.g., P4) and analytical performance-modeling methods (queueing theory, Little's Law, bandwidth-delay sizing).
• Ability to drive independent analysis and influence architectural direction using data.

Nice-to-have:

• Extensive experience (e.g., 15+ years) in networking datapath architecture and offload design.
• Experience with hardware description languages and ASIC simulation flows (SystemVerilog, VHDL) and post-silicon validation/model-to-hardware correlation.
• Experience designing high-performance NVMe-over-Fabric offloads and programmable datapath engines (programmable parsers, match-action).
• Experience with high-level synthesis, PPA-driven microarchitectural optimization, and performance modeling frameworks (e.g., SystemC).
• Experience designing schedulers, arbiters, and traffic-management hardware (WRR/DWRR, hierarchical schedulers, shapers/policers).
• Experience developing Python-based automation for simulation orchestration, regression testing, and performance analysis.
• Familiarity with GPU/ML programming and multi-threaded programming paradigms.

Education Requirements

Minimum: Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Preferred: PhD in Computer Science, Computer Engineering, or Electrical Engineering. The posting explicitly allows equivalent practical experience in lieu of a degree.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.