DPU IO Architect, Infrastructure Silicon

Job Title

DPU IO Architect, Infrastructure Silicon

Role Summary

Design and own the I/O subsystem and hardware/software interface for data processing units (DPUs) used in hyperscale data centers. Work across architecture, RTL, firmware, drivers, design verification, and post-silicon bring-up to define register/programming models, DMA/descriptor interfaces, doorbells, offload engines, I/O virtualization, confidential computing, and system management.

The role sits in Meta's Infrastructure Silicon organization and requires driving architecture from early path-finding through implementation and silicon bring-up while balancing performance, power, and area trade-offs.

Experience Level

Senior level. Requires roughly 8+ years of relevant industry experience (architecting I/O and system subsystems for NIC/DPU or comparable ASICs).

Responsibilities

Primary responsibilities include specifying interfaces and trade-offs and collaborating with firmware, software, and design teams to deliver a production I/O subsystem.

• Own I/O subsystem architecture for DPUs: PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management from path-finding through silicon bring-up.
• Decide partitioning of functionality across hardware, firmware, and host software and design the interfaces between them.
• Define hardware/software interfaces: registers, programming models, descriptors, doorbells, error and interrupt models, and offload interfaces for firmware/drivers.
• Collaborate closely with firmware, driver, RTL, DV, PD, and software teams; evolve interfaces to meet changing requirements.
• Quantify and justify performance, power, and area trade-offs; partner with performance modeling for deeper analysis.
• Support design, verification, PD, and post-silicon teams to resolve integration and bring-up issues.

Requirements

Must-have technical experience and knowledge required to perform the role.

• 8+ years architecting I/O and system subsystems and their hardware/software interfaces (register/programming models, DMA/descriptor interfaces, doorbells, offload interfaces) for NIC/DPU or comparable ASICs.
• Deep experience with PCIe data link and transport protocols, TLP formats, transaction types, and ordering rules.
• Experience with I/O virtualization technologies such as SR-IOV and SIOV, and PCIe capabilities like Advanced Error Reporting and Downstream Port Containment.
• Familiarity with on-chip scheduling/arbitration and QoS mechanisms (schedulers, arbiters, traffic shaping, rate limiting) and their latency/bandwidth impacts.
• Knowledge of symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM).
• Understanding of x86 and/or ARM system architecture, virtualization technologies, IOMMUs, and interrupt virtualization.
• Experience with data center workloads and their I/O characteristics; ability to drive architectural decisions backed by data.
• Nice-to-have: designing PCIe endpoints/root complexes, HDLs and ASIC simulation flows, Python automation for simulation/regression, performance modeling infrastructure, system-management protocols (I2C, I3C, MCTP, SPI/eSPI), DMA/offload accelerator design, and post-silicon performance validation.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Preferred: Master's or PhD in Computer Science, Computer Engineering, or Electrical Engineering. (Source also cites "or equivalent practical experience" and a PhD as preferred.)

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.