Display Synthesis Engineer, Senior

Job Title

Display Synthesis Engineer, Senior

Role Summary

Responsible for synthesis and implementation of display subsystem blocks, developing signoff-quality constraints and power intent, and delivering timing-closed, low-power netlists. Works within the Hardware Engineering team in Bangalore and coordinates with design, DFT and physical-design teams.

Focuses on execution efficiency and optimizations in area, power and performance while maintaining high quality standards.

Experience Level

Senior — the posting targets senior-level candidates. The description references leadership responsibilities and multiple statements indicate 5+ years for senior/lead roles; minimum experience requirements vary by degree (see Education Requirements).

Responsibilities

Primary duties include:

• Develop signoff-quality synthesis and STA constraints for complex, multi-clock display blocks.
• Implement power intent and low-power flows (UPF) and validate low-power checks.
• Run synthesis and implementation flows using industry tools and analyze results for timing, area and power trade-offs.
• Perform formal and equivalence checks (LEC), memory BIST insertion, and DFT/DFR validation.
• Use Synopsys and Cadence toolchains for synthesis and timing signoff and resolve timing-closure issues.
• Develop and maintain automation and analysis scripts; debug design flows and ECOs.
• Collaborate with RTL design, physical design and DFT teams to deliver netlists and resolve integration issues.
• Lead, mentor and grow a team of implementation engineers; manage multiple time-sensitive projects.

Requirements

Technical must-haves and preferred skills.

• Hands-on experience with Synopsys DCG / Genus / Fusion Compiler or equivalent synthesis tools.
• Hands-on experience with Synopsys PrimeTime for STA and constraint development.
• Experience with Cadence Conformal LEC and Conformal Low Power flows and UPF-based low-power implementation.
• Proven ability in timing closure for multi-clock-domain designs, including MCMM synthesis and optimization.
• Familiarity with low-power techniques (e.g., clock gating) and power optimization flows.
• Scripting and automation skills (Tcl; experience with Python or Perl desirable).
• Experience handling ECOs, formal verification, and working independently with design/DFT/PD teams.
• Strong communication skills and demonstrated ability to lead cross-functional execution.
• Nice to have: RTL development or physical-design experience; experience with MEMBIST, CLP, DFT DRC.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field (typically with 2+ years of hardware engineering experience); OR Master's degree in the same fields (typically with 1+ year of hardware engineering experience); OR PhD in a related field. The posting also references 5+ years for senior/lead roles. Equivalent practical experience is acceptable where specified.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.