Job Title
Director, Yield Architecture & Engineering
Role Summary
Senior technical and people leader on the Yield Management team responsible for embedding Design for Yield into architecture and design, advancing automation and AI across yield analysis and debug workflows, and leading a high-performing yield analysis and debug organization.
Experience Level
Senior. Minimum qualifications specify degree-dependent experience: Bachelor's +8 years, Master's +7 years, or PhD +6 years in ASIC design, verification, validation, integration, or related work.
Responsibilities
Lead strategy, systems, and people to improve product yield and manufacturability across complex silicon programs.
- Define and drive Design for Yield (DFY) principles across architecture, design, product, and test teams to improve defect tolerance, redundancy, diagnosability, and manufacturability.
- Lead development and deployment of automation, analytics, and AI-driven systems for yield analysis, root-cause identification, and decision support.
- Manage, coach, and develop the yield analysis/debug team, setting goals and removing organizational friction to enable high performance.
- Establish metric-driven operating mechanisms, standardized workflows, and continuous improvement practices for yield management.
- Influence cross-functional partners (design, manufacturing, test, product, data, executives) to align yield priorities with business goals.
Requirements
Concise list of required and preferred technical and leadership capabilities. Degree and specific degree-year combinations are summarized under Education Requirements below.
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Must-have: Hands-on experience in ASIC design, verification, validation, integration, or closely related engineering roles; demonstrated yield analysis or post-silicon debug experience.
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Must-have: Proven record of driving yield improvements across complex silicon products and strong practical understanding of manufacturability and debug tradeoffs.
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Must-have: Experience building or scaling automation, analytics, or AI-driven workflows that accelerate debug and improve engineering productivity.
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Must-have: Strong technical communication and cross-functional collaboration skills; ability to influence technical and business stakeholders.
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Nice-to-have: Substantial semiconductor or hardware engineering experience in product/engineering roles and prior experience implementing metric-driven operating practices.
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Nice-to-have: Demonstrated people leadership and experience developing and scaling engineering teams.
Education Requirements
Minimum qualifications: Bachelor's degree in Science, Engineering, or a related field plus 8+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or a related field plus 7+ years of relevant experience; OR PhD in Science, Engineering, or a related field plus 6+ years of relevant experience. Preferred fields include Engineering and Computer Science.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

Date Posted: 2026-06-28