Director, Verification

Job Title

Director, Verification

Role Summary

Lead Kepler's pre-silicon verification and post-silicon validation efforts for SoC/ASIC products. This role coordinates architecture, RTL design, and software teams to deliver verification plans, tapeout signoff, and production validation.

Responsible for building and managing a high-performing verification and emulation organization and for defining scalable verification methodologies and infrastructure.

Experience Level

Senior - requires extensive leadership and technical experience; the role specifies 15+ years of hands-on VLSI front-end verification experience.

Responsibilities

Key responsibilities include ownership of verification strategy, execution, and team leadership.

• Own end-to-end pre-silicon verification strategy: test plans, testbench development, automated flows, regressions, coverage closure, and tapeout signoff.
• Define and run verification plans covering functional coverage, assertions, constrained-random stimulus, formal verification, and AI-assisted flows.
• Co-lead model-based testing, emulation, and FPGA prototyping for pre-silicon verification and software validation.
• Collaborate with architecture, RTL design, DFD, and software teams to align verification with design intent.
• Define and execute post-silicon bring-up, validation, debug, and production qualification activities.
• Develop verification IP and protocol checkers; set UVM-based testbench architecture standards and a coverage-driven methodology.
• Build and maintain regression infrastructure including nightly/weekly pipelines, coverage merge, and automated triage.
• Track and publish verification health metrics (coverage, assertion density, regression health) and run milestone reviews.
• Recruit, lead, and mentor verification and emulation engineers.

Requirements

Must-have technical skills and leadership experience. Nice-to-have items listed separately.

• 15+ years of hands-on VLSI front-end verification experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in UVM-based verification: testbench architecture, scoreboarding, coverage modeling, and constrained-random verification.
• Strong SystemVerilog skills including interfaces, clocking blocks, SVA, covergroups, and testbench development.
• Thorough understanding of SoC-level verification challenges: CDC, power-aware verification (UPF), memory subsystems, interrupt and reset validation.
• Solid knowledge of industry-standard on-chip and memory protocols and VIP integration.
• Hands-on experience with formal verification and simulation tools.
• Hands-on experience with coverage closure: functional, code, and assertion coverage.
• Good scripting skills (Python, Perl, Shell, Makefile).
• Exposure to hardware/software co-verification (TLM/SystemC).
• Experience with post-silicon validation, debug, and production test correlation.
• Proven leadership and communication skills with a track record of delivering products from pre-silicon verification through production release.

Nice-to-have

• Experience with emulation platforms.
• Familiarity with ML-assisted verification (coverage prediction, test prioritization).
• Understanding of DFT-aware verification (scan, BIST, JTAG) and debug architecture.
• Knowledge of verification challenges in 3D integrations.
• Familiarity with AI workloads and their memory demands.
• Prior startup experience with lean teams and aggressive timelines.

Education Requirements

B.Tech, M.Tech, or MS in Electrical Engineering, Electronics, VLSI Design, or a related field.

About the Company

Company: Keplercompute

Headquarters: San Jose, California, United States

Kepler is a semiconductor startup developing a new class of AI memory and logic using advanced materials and 3D architectures to build UHBM-based 3D-memory AI accelerator platforms. The team includes experienced semiconductor veterans and partners with foundries and customers to move lab technologies toward production.