Director, Silicon Design Engineering

Job Title

Director, Silicon Design Engineering

Role Summary

Lead timing and physical design efforts for next-generation System-on-Chip (SoC) products within Intel's Central Engineering Group. Work with architecture, clocking, logic, and full-chip teams to define and drive timing methodologies, clocking flows, and timing optimization across complex SoC designs.

Experience Level

Senior — role expects significant domain experience. The posting specifies guidance: at least 12 years with a Bachelor's, 8 years with a Master's, or 6 years with a PhD in timing analysis, physical design, or a related domain.

Responsibilities

Primary responsibilities focus on timing analysis, constraint development, flow definition, and cross-team integration for high-performance, low-power SoCs.

• Perform comprehensive static timing analysis and timing optimization at block and chip level.
• Generate, validate and maintain timing constraints; diagnose and fix timing violations.
• Develop timing rollups and validate design functionality with optimized performance and power.
• Define PVT (process, voltage, temperature) conditions and binning-based timing scenarios.
• Collaborate with clocking and full-chip teams to maintain clock balance and resolve timing issues.
• Define and validate advanced SoC clocking flows and timing methodologies with architecture and logic teams.
• Drive development of methodologies and timing models to improve physical design efficiency.
• Ensure clock network guidelines and drive flow development for chip integration.

Requirements

Must-have technical skills and organizational requirements; education details are in the Education Requirements section below.

• Extensive experience with static timing analysis, timing constraint generation, and timing optimization techniques.
• Experience with physical design tools, flows, and timing analysis methodologies (TFM).
• Deep knowledge of SoC clocking, timing budgeting, and constraint adaptation.
• Proficiency in scripting (TCL) for automation and design optimization.
• Understanding of digital design fundamentals, power and performance analysis, and optimization approaches.
• Experience working on large-scale, complex SoC designs and cross-functional collaboration.
• Position of Trust requirement: must consent to and pass an extended background investigation as required for the role.

Nice-to-have:

• Exposure to signal and power integrity analysis and optimization.
• Experience with advanced process nodes and leading EDA tools.
• Proven track record of developing timing-aware methodologies at chip scale.

Education Requirements

Requires a Bachelor's (BS) in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. The posting also references advanced degree levels when mapping experience to seniority (Master's or PhD reduce required years of experience). Equivalent experience is accepted per job requirements.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.