Director, Physical Design (Custom Silicon Group)
QualcommJob Title
Director, Physical Design (Custom Silicon Group)
Role Summary
Lead the physical design organization for Custom Silicon Group to deliver high-performance SoCs from architecture through tapeout and production readiness. The role combines technical leadership in PnR and signoff with cross-functional coordination across RTL, verification, CAD, integration, firmware, software and validation teams.
Experience Level
Senior-level. The posting provides varying guidance: degree-dependent thresholds of ~6–8+ years and an alternate statement requesting 18–20+ years of Physical Design/VLSI experience.
Responsibilities
Key responsibilities include technical and organizational leadership across the silicon lifecycle and direct ownership of physical design and signoff.
- Lead and manage multi-site, cross-functional physical design teams.
- Drive PnR implementation: floorplanning, placement, CTS, routing and post-route closure.
- Ensure timing, power, area convergence and signoff integrity (STA, power analysis, formal/functional verification, physical verification).
- Resolve constraints, verification, STA and tapeout issues in coordination with RTL, verification, CAD and integration teams.
- Provide technical leadership in design reviews and executive-level customer engagements.
- Support pre-sales and business development by evaluating technical feasibility and providing design expertise.
- Coordinate cross-discipline resolution of customer-reported issues through design, verification, firmware, software and validation.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- Proven experience leading physical design teams across multiple sites and functions.
- Hands-on expertise in floorplanning, placement, clock tree synthesis (CTS) and PnR flows through tapeout on advanced nodes.
- Mandatory signoff knowledge: static timing analysis (STA), power analysis, functional/format verification, low-power verification and physical verification.
- Deep understanding of sub-micron challenges: leakage, signal integrity, DFM and low-power/high-performance optimization.
- Experience collaborating with RTL, verification, CAD, integration and system teams to achieve design closure.
- Customer-facing experience, including design reviews and pre-sales technical evaluations.
- Preferred: direct experience with leading-edge process nodes (e.g., 2nm/3nm/4nm/5nm) and extensive timing signoff background.
Education Requirements
Requires a Bachelor’s, Master’s or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field (the posting lists degree-dependent experience thresholds). The role accepts these technical degrees; the posting also references very senior experience levels (up to ~18–20+ years) in some sections.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
