Director, Physical Design

Job Title

Director, Physical Design

Role Summary

Lead and execute full-chip and complex-subsystem physical design for a next-generation UHBM-based 3D-memory AI accelerator. This role owns the physical design flow from netlist ingestion through GDSII signoff and drives methodology, tool selection, and PPA trade-offs across architecture, RTL, packaging, foundry, and design-service partners.

High-impact technical leadership role managing internal engineers and external design-service partners; includes responsibility for floorplanning, timing closure, power and SI, 3D-IC constraints, and tapeout readiness. Kepler offers a comprehensive benefits package for eligible employees.

Experience Level

Senior — typically 15–20 years of progressive, hands-on ASIC/SoC physical design experience; proven track record of silicon tapeouts and productization.

Responsibilities

The primary responsibilities focus on technical leadership, execution, cross-functional coordination, and team delivery for full-chip and multi-block physical design.

• Own full-chip physical implementation from netlist to GDSII: floorplanning, placement, CTS, routing, ECO, and signoff.
• Drive PPA and timing closure decisions; resolve critical path, congestion, and DRC challenges at advanced nodes.
• Define and implement floorplanning strategies: partitioning, macro placement, pin assignment, power domains, and TSV planning for 3D-memory stacks.
• Develop power-integrity strategy and perform IR drop/EM analysis for compute die and 3D-memory interfaces.
• Lead clock-tree synthesis strategy and multi-corner CTS closure using CCOPT and advanced routing methodologies.
• Coordinate STA signoff and PD-driven ECOs in close collaboration with synthesis, STA, DFT, and verification teams.
• Ensure physical verification and clean tapeout using DRC/LVS/ERC flows (Calibre/IC Validator) and manage foundry/package constraints.
• Lead delivery and hardening of IP (GDSII, timing models, LEF/DEF) and support post-silicon bring-up and validation.
• Manage and mentor a team of physical-design engineers across internal and external partners; own resource planning and tapeout readiness reviews.

Requirements

Must-have technical skills, experience, and leadership attributes required for success in this role.

• 15–20 years hands-on ASIC/SoC physical design experience with multiple silicon tapeouts and productizations.
• Expert-level proficiency with Cadence Innovus Implementation System; experience with Cadence Genus iSpatial/Innovus flows preferred; familiarity with Synopsys ICC2/Fusion is a plus.
• Deep experience with advanced-node physical design (7nm/5nm/3nm), FinFET design rules, and routing challenges.
• Strong CTS knowledge (mesh, spine, H-tree, shielded routing), multi-corner CTS and CCOPT-based optimization.
• Proven ability in timing-driven placement, congestion-aware routing, SI-aware signoff, and STA/ECO execution.
• Physical verification signoff experience (DRC/LVS/ERC) using Mentor Calibre or IC Validator and interaction with synthesis and STA flows.
• Experience with IP hardening and delivering GDSII, timing models, and LEF/DEF to internal or external customers.
• Experience with NoC/Fabric/AXI interconnect physical implementation and high-performance on-chip network placement/routing.
• Experience with DFT-aware physical design (scan routing, BIST placement, JTAG/boundary-scan integration) and low-power UPF-based implementation techniques.
• Excellent leadership, communication, and stakeholder management skills; proven ability to drive complex PD programs in a fast-paced startup environment.

Nice-to-have:

• Exposure to 3D-IC, chiplet, or advanced packaging (HBM base die, EMIB, UCIe) and TSV-based PD constraints.
• DDR/HBM PHY physical-design experience and familiarity with analog/mixed-signal coexistence.
• Scripting and automation skills (Tcl for Innovus, Python, Perl) for flow development and PD automation.
• Prior startup experience delivering complex designs with small teams and aggressive schedules.

Education Requirements

B.E./B.Tech, M.Tech, or MS in Electronics, Electrical Engineering, VLSI, or a related discipline (specified in the source). Degree in a relevant technical field is expected.

About the Company

Company: Keplercompute

Headquarters: San Jose, California, United States

Kepler is a semiconductor startup developing a new class of AI memory and logic using advanced materials and 3D architectures to build UHBM-based 3D-memory AI accelerator platforms. The team includes experienced semiconductor veterans and partners with foundries and customers to move lab technologies toward production.