Director of Engineering, ML Hardware Design & Architecture
QualcommJob Title
Director of Engineering, ML Hardware Design & Architecture
Role Summary
Lead definition and analysis of next-generation machine-learning hardware accelerator architectures, with emphasis on computer-vision workloads for mobile and emerging products. Own micro-architecture, PPA tradeoffs, and delivery of HW IP across RTL, verification, synthesis and physical design teams.
Work cross-functionally with software, systems, product planning and global engineering teams to deliver production-quality ML solutions.
Experience Level
Senior-level (Director). The posting provides multiple experience guidelines: one section lists an MS plus 15+ years; alternative minimums state Bachelor's +8 years, Master's +7 years, or PhD +6 years of relevant experience.
Responsibilities
Core responsibilities include architecture, specification, and technical leadership for ML accelerator hardware:
- Architect high-performance, power-efficient ML accelerators for vision (image classification, object detection, video analytics).
- Analyze and optimize performance, power, and area (PPA) tradeoffs across the design stack.
- Define hardware micro-architecture to efficiently map ML algorithms to silicon.
- Lead HW IP development and coordinate RTL design, verification, synthesis and physical design to improve PPA.
- Use models, simulators, profilers, and silicon measurements to justify architectural decisions quantitatively.
- Apply knowledge of CPUs, GPUs, DSPs, memory subsystems and bandwidth analysis to system-level design.
- Collaborate with software and systems teams to ensure HW/SW integration and product alignment.
- Communicate technical plans and results to engineering leadership and stakeholders.
- Drive innovation and file patents for novel hardware solutions.
Requirements
Must-have technical skills and experience. Education details are summarized under Education Requirements below.
- Proven hardware development experience for ML, multimedia, or accelerator technologies (vision, imaging, video).
- System/SoC development experience for chipset products and familiarity with SoC bus, interconnect, and memory technologies.
- Experience in architecture or micro-architecture of ML or multimedia cores.
- VLSI design and verification experience (Verilog/SystemVerilog, HLS) and familiarity with synthesis/physical design flow.
- Proficiency in C/C++ and SystemC for modeling; experience with ML frameworks and accelerator standards (e.g., TensorFlow Lite, ONNX).
- Hands-on experience with simulators, performance and power models, profiling and PPA analysis.
- Scripting and automation skills for design and verification workflows.
- Demonstrated technical leadership and ability to work across global, cross-functional teams.
Preferred:
- Deep domain knowledge in ML for vision and neural network architectures for image/video processing.
- Experience collaborating across time zones and with geographically distributed teams.
- Track record working with synthesis and physical design teams to optimize HW IP PPA.
- Strong written and verbal communication and documentation skills.
Education Requirements
The posting references multiple degree-based minimums: one section specifies an MS degree with 15+ years industry experience. Alternate stated minimums are: Bachelor's in Computer or Electrical Engineering, Computer Science, or a related field with 8+ years; Master's in those fields with 7+ years; or PhD with 6+ years. The posting also allows equivalent related work experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
