Director of Design Verification

Job Title

Director of Design Verification

Role Summary

Lead and own design verification (DV), emulation, and pre-silicon verification across multiple complex SoC programs within Marvell Custom Solutions. The role drives DV strategy, architectures, tool selection, and execution to deliver production-quality ASICs in advanced process nodes.

Experience Level

Senior (Director-level). The role expects extensive leadership experience in ASIC verification and program delivery; the posting specifies very senior experience (see Education Requirements for explicit years-of-experience guidance).

Responsibilities

Key responsibilities include planning, executing, and improving verification across SoC programs and building a high-performing DV organization.

• Lead DV, emulation, and pre-silicon verification execution across multiple programs with a zero-defect mindset.
• Define DV scope, methodology, and verification strategies that scale for complex SoCs.
• Architect verification testbench and infrastructure; define and drive implementation of TB architectures.
• Set program timelines and goals; monitor progress and take decisive action to keep execution on track.
• Collaborate with Architecture, Design, DFT, PD, Firmware, and System teams to ensure successful delivery from specification to tape-out.
• Lead tool evaluation and selection; advance the DV toolset and flow.
• Drive productivity improvements across verification flows, including major workflow changes when required.
• Monitor industry DV trends and adapt verification approaches, particularly for PCIe and memory technologies.
• Recruit, develop, and retain a global, high-performance verification team and address training and career development needs.

Requirements

Must-have technical and leadership qualifications. Preferred items are listed under "Nice-to-have." Educational degree requirements are summarized in the Education Requirements section below.

• Deep understanding of the full ASIC development lifecycle from architecture through tape-out and production.
• Proven ability to lead and scale ASIC verification teams across global design centers.
• Track record of delivering production-grade ASICs on schedule.
• Strong understanding of SoC architecture, including processor cores, memory subsystems, and peripheral interfaces.
• Strong cross-functional leadership and influence skills to align Architecture, Design, DFT, PD, FW, and System teams.
• Excellent communication, interpersonal, and presentation skills for interfacing with senior leadership and customers.
• Highly motivated, self-driven, and curious about emerging verification methodologies and technologies.

Nice-to-have

• Experience with emulation platforms and pre-silicon validation strategies.
• Familiarity with advanced verification techniques: formal verification, hardware-software co-verification, and post-silicon validation.
• Background in high-speed interface verification (112G+ SerDes) and interfaces such as PCIe Gen6/7 and CXL 3.0.
• Knowledge of DDR, LPDDR, and HBM memory technologies.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, or related field with 20+ years of relevant professional experience; OR Master's degree or PhD in Computer Science, Electrical Engineering, or related field with 15+ years of relevant experience. The posting specifies degree fields in CE, EE, CS or related technical disciplines and presents degree+experience combinations as the hiring guideline.

Reasonable accommodation requests: contact Marvell HR Helpdesk at TAOps@marvell.com.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.