Director, Memory Design

Job Title

Director, Memory Design

Role Summary

Lead the architecture, RTL implementation, verification, and tapeout signoff for a custom memory controller targeting Kepler's UHBM-based 3D-memory AI accelerator. This role sits at the intersection of custom DRAM architecture, digital logic design, and SoC integration.

Work cross-functionally with SoC architects, packaging, physical design, verification, and vendor partners to deliver a low-latency, PPA-optimized memory subsystem for AI inference workloads.

Experience Level

Senior — 15–20 years of hands-on experience in memory controller architecture and RTL design, with multiple SoC tapeouts involving complex memory subsystems.

Responsibilities

Ownership of the memory controller design life cycle and technical leadership across related integration activities.

• Define end-to-end memory controller architecture, micro-architecture, RTL, verification plan and tapeout signoff.
• Architect and implement a low-latency access path optimized for distributed TSV-based 3D DRAM topology.
• Create or substantially modify existing controller designs for custom command/address protocols, timing, refresh, interleaving and power management.
• Specify and optimize the TSV interface architecture, PHY interaction, timing budgets, and ECC strategy.
• Develop micro-architecture specs for scheduler, command/address path, datapath, ECC engine, refresh controller and training state machines.
• Implement synthesis-ready, lint-clean, CDC-safe SystemVerilog RTL and drive implementation convergence (LINT, CDC/RDC, LEC, synthesis, timing closure).
• Produce and validate SDC timing constraints, provide floorplanning and pin-placement guidance, and support physical-design interactions.
• Work with verification, emulation and post-silicon teams for pre-silicon bring-up, validation, and characterization.
• Engage with DRAM technology partners and IP vendors to ensure controller-DRAM compatibility and compliance.
• Document design standards, maintain interface and micro-arch specs, and mentor junior engineers.

Requirements

Must-have technical skills, tools, and demonstrable track record delivering memory controllers for complex SoC designs.

• 15–20 years hands-on memory controller architecture and RTL design experience with multiple successful SoC tapeouts.
• Deep expertise in DRAM controller subsystems: scheduler, command/address path, datapath, ECC, refresh management, power-down and training state machines.
• Proven experience modifying/implementing controller RTL to meet custom product requirements (beyond IP integration).
• Strong knowledge of DRAM protocols and timing (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3 or custom) and ability to adapt to non-standard specs.
• Expertise in 3D memory integration challenges: TSV connectivity, die stacking, signal integrity, timing and power implications.
• Hands-on experience with front-end implementation flows: LINT, CDC/RDC, LEC, synthesis (Genus/Design Compiler), SDC constraint development and formal verification.
• Proficiency in SystemVerilog for clean, synthesis-ready RTL and strong scripting skills (Python, Perl, Tcl) for automation and analysis.
• Experience designing and implementing ECC architectures (SEC-DED, ChipKill, or custom) for memory reliability.
• Ability to make VLSI PPA trade-offs (latency vs. bandwidth, area vs. power) with evidence-based decisions for AI workloads.
• Demonstrated ability to lead across teams and deliver complex design blocks end-to-end in an engineering organization.

Nice-to-have:

• Hands-on HBM base-die or custom base-die memory controller and PHY interaction experience.
• Experience with custom/proprietary DRAM interfaces beyond JEDEC, CXL implications, and memory performance modeling.
• Exposure to PHY-level training (DQ/DQS), impedance calibration, chiplet/2.5D/3D-IC integration, and post-silicon bring-up.
• Prior startup experience delivering custom silicon in lean teams.

Education Requirements

B.Tech, M.Tech, MS or PhD in Electrical Engineering, Electronics & Communication, Computer Engineering, or a related discipline (as listed in the posting).

About the Company

Company: Keplercompute

Headquarters: San Jose, California, United States

Kepler is a semiconductor startup developing a new class of AI memory and logic using advanced materials and 3D architectures to build UHBM-based 3D-memory AI accelerator platforms. The team includes experienced semiconductor veterans and partners with foundries and customers to move lab technologies toward production.