Director, Front End Design

Job Title

Director, Front End Design

Role Summary

Lead and own pre-silicon RTL design and implementation for Kepler's products from micro-architecture through tapeout and post-silicon validation. This is a hands-on leadership role responsible for RTL execution, IP integration, verification coordination, physical-design interaction, and team development.

The role reports to senior engineering leadership and requires cross-functional collaboration with architecture, verification, physical design, DFT and software teams.

Experience Level

Senior - requires extensive leadership and technical experience; the posting specifies 15+ years of hands-on VLSI front-end RTL design experience.

Responsibilities

Manage RTL design execution end-to-end and lead a team of RTL/IP engineers. Key responsibilities include:

• Own pre-silicon RTL design lifecycle: micro-architecture, RTL freeze, synthesis handoff and tapeout signoff.
• Define RTL execution strategy: coding guidelines, partitioning, clock/reset architecture, low-power strategy and DFT integration.
• Track and present design metrics (RTL quality, lint/CDC status, synthesis QoR) at milestone reviews.
• Drive IP integration and ensure IP quality meets integration standards.
• Coordinate cross-functional integration with architecture, verification, physical design, DFT and software teams.
• Establish RTL best practices, review standards and sign-off infrastructure.
• Plan for bring-up, post-silicon validation, debug and production qualification.
• Recruit, build, mentor and lead RTL design and IP engineering staff.

Requirements

Must-have technical skills, experience and leadership capabilities:

• 15+ years of hands-on VLSI front-end RTL design experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in RTL design and micro-architecture (SystemVerilog/Verilog) with strong PPA optimization skills.
• Strong knowledge of low-power design methods: UPF/CPF, clock and power gating, retention and isolation.
• Hands-on experience with synthesis flows and timing closure.
• Skilled with industry-standard lint, CDC/RDC and formal verification tools.
• Solid knowledge of DFT methods: scan insertion, ATPG, MBIST and JTAG.
• Strong understanding of SoC-level issues: clock domain crossings, reset architecture, power domains and memory subsystems.
• Experience with post-silicon validation, debug and production test correlation.
• Proficient scripting skills (Python, Perl, Shell, Tcl).
• Proven leadership and communication skills in fast-paced environments.

Nice-to-have:

• Familiarity with AI workloads and memory demands; background in high-bandwidth memory subsystem design.
• Exposure to hardware/software co-design (TLM/SystemC) and emulation platforms.
• Experience with PD-driven RTL optimization, 3D innovations, or ML-assisted design optimization tools.
• Prior startup experience with lean teams and aggressive timelines.

Education Requirements

B.Tech, M.Tech, MS or PhD in Electrical Engineering, Electronics, VLSI Design or a related field (as specified in the posting).

About the Company

Company: Keplercompute

Headquarters: San Jose, California, United States

Kepler is a semiconductor startup developing a new class of AI memory and logic using advanced materials and 3D architectures to build UHBM-based 3D-memory AI accelerator platforms. The team includes experienced semiconductor veterans and partners with foundries and customers to move lab technologies toward production.