Director, Design Verification

Job Title

Director, Design Verification

Role Summary

Lead the design verification organization for DSP IP and SoC verification across multiple sites, delivering verification strategy, testbench architectures, and cross‑functional collaboration for data‑center, AI, and telecom SoCs.

Coordinate with architecture, design, DFT, PD, firmware and system teams to ensure designs meet customer specifications and schedules.

Experience Level

Senior — management-level role. Experience guidance varies by degree: PhD 8–10 years; MS 10–12 years; BS 15+ years. Requires demonstrated experience managing large engineering teams and SoC verification programs.

Responsibilities

Lead verification execution, strategy, and team development for DSP IP and SoC projects.

• Define and drive verification execution timelines and priorities with stakeholders.
• Set goals, monitor progress, and take corrective actions to meet schedules.
• Define DV methodology and verification strategies; establish and evolve testbench architectures (UVM/SystemVerilog).
• Oversee verification testbench development and integration using C/C++ and DPI where applicable.
• Collaborate with Architecture, Design, DFT, PD, Firmware, and System teams for successful product delivery.
• Drive continuous productivity improvements, including incremental and forklift changes.
• Hire, build, and retain a high‑performance distributed engineering team; establish new sites as needed.
• Provide ongoing training and development for team members.
• Participate in problem solving and quality improvement activities using data-driven analysis.

Requirements

Must-have technical leadership, verification expertise, and people management skills.

• Proven experience managing large engineering teams (manages more than 20 engineers across multiple sites).
• Strong background in SoC verification and testbench development using UVM and SystemVerilog.
• Proficiency in C/C++ and DPI integration for verification environments.
• Deep understanding of verification methodology: object‑oriented techniques, directed/random testing, coverage, and gate‑level simulation.
• Experience collaborating cross-functionally with DFT, PD, firmware, and system engineering teams.
• Track record of hiring, mentoring, and retaining engineering talent.
• Effective interpersonal, communication, and stakeholder management skills.
• Strong analytical skills, attention to detail, and ability to draw valid conclusions from datasets.

Education Requirements

Degree required: Bachelor's, Master’s, or PhD in Computer Science, Electrical Engineering, or a related technical field. Experience guidance from the posting: BS +15+ years; MS +10–12 years; PhD +8–10 years. Equivalent practical experience may be considered.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.