Director, Custom HBM Design and Architecture

Job Title

Director, Custom HBM Design and Architecture

Role Summary

Lead the design, integration, and delivery of next-generation HBM SoC logic die for AI/ML applications. Align architecture, RTL design, verification, physical design, firmware, and product teams to meet performance, power, area, schedule, and quality targets.

Responsible for technical strategy, execution across multiple product generations, and building a high-performing RTL design and integration organization.

Experience Level

Senior - preferred 15+ years of relevant SoC design and technical leadership experience.

Responsibilities

Accountable for technical direction and successful delivery of RTL and SoC integration across the product lifecycle. Key responsibilities include:

• Analyze system-level hardware/software interactions to identify bottlenecks in AI/ML workloads and HBM-based systems.
• Drive HBM architecture and technology decisions; implement proofs-of-concept to validate approaches.
• Translate architectural and micro-architectural specifications into robust, production-quality RTL across teams.
• Own RTL deliverables through development, integration, validation, and silicon bring-up.
• Make trade-offs across performance, power, area, schedule, and risk; implement mitigation plans.
• Proactively identify execution risks and coordinate cross-team mitigations across design phases.
• Recruit, mentor, and scale a high-performing RTL design and integration team; develop future technical leaders.

Requirements

Core technical and leadership requirements. Items marked as preferred are optional but advantageous.

Must-have:

• Proven experience leading large-scale SoC design teams delivering complex SoCs to advanced process nodes (e.g., TSMC).
• Deep expertise in RTL design, SoC integration, and full RTL-to-GDS flows, including synthesis, timing, and signoff considerations.
• Experience integrating complex IP subsystems (controllers, NOC, microcontrollers, PHY-adjacent logic, RAS, MBIST, interfaces).
• Solid understanding of SoC architecture, clocking, reset, power management, and system-level trade-offs.
• Experience with pre-silicon validation, hardware emulation, and post-silicon debug methodologies.
• Familiarity with EDA tools and scripting languages such as SystemVerilog, Python, and TCL.

Nice-to-have / Preferred:

• Knowledge of DRAM/HBM systems and JEDEC standards.
• Demonstrated success driving multiple tape-outs and cross-functional SoC programs.
• Experience building and managing global engineering teams; strong leadership and communication skills.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.