Director, ASIC Design & Front-End Implementation

Job Title

Director, ASIC Design & Front-End Implementation

Role Summary

Lead HPE's ASIC Design and Front-End Implementation organization responsible for delivering next-generation networking ASICs from architecture through tapeout, silicon bring-up, and product deployment. Work cross-functionally with Architecture, Verification, Physical Design, Software/SDK, Post-Silicon Engineering, Product Management, and Marketing to meet performance, power, area, cost, quality, and schedule objectives.

Experience Level

Senior - requires 15+ years of ASIC development experience, including 8+ years leading engineering teams and managers.

Responsibilities

Manage technical execution, program delivery, and people leadership across multiple ASIC programs.

• Lead RTL design and microarchitecture teams; drive design execution from architecture through RTL completion.
• Establish design methodologies, coding standards, and engineering best practices; review architectural and implementation trade-offs.
• Partner with Physical Design for floorplanning, timing closure, power optimization, DFT integration, and tapeout readiness.
• Coordinate with Verification, Emulation, Software/SDK, Post-Silicon, Product Management, and Marketing to align requirements and schedules.
• Manage program schedules, dependencies, risks, milestone assessments, and technical issue resolution through silicon bring-up and product deployment.
• Recruit, develop, and retain engineering managers and senior technical contributors; promote accountability and technical excellence.
• Drive methodology and productivity improvements via automation, CI/CD, and AI-assisted engineering tools.

Requirements

Must-have technical expertise and proven leadership in ASIC development and delivery.

• 15+ years of ASIC development experience and proven track record delivering complex ASICs from concept to production.
• 8+ years of experience leading engineering teams and managers.
• Expertise in RTL design and microarchitecture; strong Verilog/SystemVerilog skills.
• Experience with synthesis, CDC analysis, linting, timing closure, and full ASIC implementation flows.
• Strong cross-functional leadership and communication with Architecture, Verification, Physical Design, Software, Emulation, and Post-Silicon teams.
• Program management skills: schedule, dependency, and risk management across multiple ASIC programs.
• Experience with silicon bring-up, validation, and post-silicon debug (preferred).
• Track record driving methodology, automation, and productivity improvements, including AI-assisted workflows (preferred).

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.