Digital Verification Engineer
Efficient ComputerJob Title
Digital Verification Engineer
Role Summary
Own functional verification for blocks and subsystems in an SoC that includes proprietary Fabric technology. Collaborate with verification engineers, RTL designers, and architects to build testbenches, drive coverage closure, and identify issues before silicon.
Contribute to regression infrastructure and verification processes as the product moves from initial development to production.
Experience Level
Mid-level - typically requires 4+ years of ASIC/SoC design verification experience.
Responsibilities
Primary responsibilities include implementing and executing verification plans, debugging failures, and supporting sign-off activities.
- Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
- Write verification plans from design specifications in collaboration with design and architecture teams.
- Implement SystemVerilog assertions and functional coverage models; drive coverage to closure.
- Debug simulation failures and work with designers to root-cause and fix issues.
- Contribute to regression infrastructure, automation, and dashboards that track verification progress.
- Support gate-level simulation and other sign-off activities.
Requirements
Required technical skills and experience; listed as must-haves and additional desirable skills.
Must-have:- 4+ years of ASIC/SoC design verification experience, including multiple projects taken through tapeout.
- Hands-on UVM and SystemVerilog experience building and extending testbench components (agents, scoreboards, sequences) and constrained-random tests.
- Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
- Working knowledge of SystemVerilog Assertions.
- Strong debug skills using waveforms, logs, and design knowledge.
- Proficiency in Python for test automation, log analysis, and regression flows.
- Clear written and verbal communication of verification status and issues.
- C/C++ experience for reference models or DPI-based verification.
- Exposure to formal verification tools (e.g., JasperGold).
- Experience building or using AI agentic flows for DV.
- Knowledge of computer architecture or dataflow architectures.
- Exposure to power-aware verification (UPF).
Education Requirements
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
About the Company
Company: Efficient Computer
Headquarters: Austin, TX, USA
Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.
