Digital Verification Engineer

Job Title

Digital Verification Engineer

Role Summary

Develop and own the UVM testbench, functional coverage model, and nightly regression infrastructure that prove RTL implements the microarchitecture correctly for a superconducting digital chip. Work directly with the digital architect, microarchitect, and RTL designers to drive verification to tape-out quality.

Experience Level

Mid-level. No explicit years-of-experience requirement stated; the role expects engineers with production verification experience on silicon that has taped out and run.

Responsibilities

Primary responsibilities for this role include:

• Design, implement, and maintain UVM testbenches for RTL blocks and full-chip verification (drivers, monitors, scoreboards, reference models).
• Define functional coverage goals from the microarchitecture spec, track coverage, and close gaps.
• Write directed and constrained-random tests that exercise SFQ/PCL-specific behaviors and corner cases.
• Build and run the chip-level simulation environment and nightly regression infrastructure tied to coverage-closure criteria.
• Drive debug cycles with RTL engineers: determine root cause and produce artifacts (waveforms, logs, tests) to make bugs fixable.
• File, triage, and track functional bugs to closure and coordinate spec vs RTL decisions with microarchitecture owners.
• Apply formal verification (properties, equivalence, model checking) where appropriate.
• Establish verification methodology and infrastructure standards for testbench architecture, coverage discipline, and regression hygiene.

Requirements

Must-have skills and experience:

• Strong UVM and SystemVerilog verification methodology experience on production silicon that taped out and ran (academic or hobby work alone is insufficient).
• Proven track record of coverage-driven verification: defining a coverage model, closing it, and defending closure decisions.
• Working experience with formal verification tools and methodology (properties, assertions, model checking) and good judgment on when to use formal.
• Solid knowledge of the full chip design flow (RTL, synthesis, STA, back-end) and the interface between verification and implementation teams.
• Strong debugging skills with discipline to find root cause rather than symptom fixes.
• Scripting proficiency (Python, Perl, or equivalent) for testbench, regression, and reporting automation.

Nice-to-have:

• Verification experience in timing-sensitive or non-standard logic environments (high-speed custom logic, asynchronous designs, wave-pipelined blocks).
• Experience building a verification environment from scratch (first testbench, coverage model, regression).
• Background on silicon teams that shipped production chips (AI inference, HPC, networking) in a lead or principal verification role.
• Deep familiarity with formal verification flows and hardware-accelerated verification (emulation, FPGA prototyping).
• Familiarity with superconducting digital logic (PCL, SFQ, AQFP, RSFQ) is a plus.

Education Requirements

Not specified.

About the Company

Company: Snowcap Compute

Headquarters: San Francisco, CA, United States

Snowcap Compute develops commercial superconducting digital computers using Josephson junction–based PCL logic that operate at cryogenic temperatures, aiming for dramatically lower power than CMOS. The company combines expertise in quantum physics, cryogenic engineering, and semiconductor manufacturing to build production superconducting chips.