Digital Signal Processing and System Validation Engineer

Job Title

Digital Signal Processing and System Validation Engineer

Role Summary

Broadcom is seeking an engineer to design digital signal processing blocks and validate ASIC architecture for next-generation optical data-center connectivity products. The role covers pre-silicon and post-silicon validation of mixed-signal SerDes and high-speed serial-link IPs and requires cross-functional collaboration with design, test, and system teams.

Experience Level

Senior — role expects senior-level experience. Typical guidance in the posting: PhD with 7+ years or MS with 10+ years in digital signal processing design for SerDes and high-speed data center networking.

Responsibilities

Core responsibilities focus on DSP development, verification, and system-level validation for high-speed SerDes and optical interconnects.

• Design and implement digital signal processing blocks (CDR, equalizers, adaptation algorithms) for high-speed serial links.
• Translate DSP and CDR/equalization architectures into synthesizable RTL (Verilog/SystemVerilog) and verify functionality.
• Develop and execute pre-silicon and post-silicon validation plans and testbenches.
• Perform SDF-annotated simulations and correlate timing and parasitic effects between RTL and silicon.
• Run simulations and analysis using Matlab/Simulink and HDL simulators to validate algorithms and performance.
• Work with front-end and back-end flows: synthesis, CDC, static timing analysis, and DFT-ready RTL.
• Debug silicon issues, analyze performance vs. power/cost trade-offs, and recommend architectural changes.
• Collaborate with cross-functional teams and communicate technical results to engineering and management stakeholders.

Requirements

Must-have technical skills and experience required for successful performance in this role.

• Proven experience in post-silicon validation of digital and analog mixed-signal IPs.
• Deep understanding of ADCs and optical/electrical interconnect architectures (PAM4, NRZ) and related performance trade-offs.
• Experience implementing CDR and equalization algorithms and converting them to RTL for synthesis.
• Proficiency with Matlab and Simulink; strong RTL coding skills in Verilog/SystemVerilog.
• Experience with front-end verification tools such as NCVerilog/NCSIM, Simvision, and Spyglass.
• Familiarity with DFT concepts (scan), writing DFT-friendly RTL, and working with synthesis/CDC/STA flows.
• Experience with SDF-annotated simulations and understanding of parasitic delay effects.

Nice-to-have:

• Experience with high-speed ADC, FFE/DFE, and PAM4-specific adaptation algorithms.
• Experience or exposure to Verilog-AMS, behavioral analog models, and SI/PI modeling for high-speed designs.
• Prior work on logic optimization for low power, timing margin improvements, and DFT-driven design.
• Strong written and verbal communication skills and experience coordinating across teams.

Education Requirements

MS in Electrical Engineering or Computer Engineering with 10+ years of relevant DSP/SerDes experience, or PhD with 7+ years of relevant experience in digital signal processing design for SerDes and high-speed data center networking.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.