Digital Signal Processing and System Validation Engineer

Job Title

Digital Signal Processing and System Validation Engineer

Role Summary

Broadcom seeks a senior engineer to design digital signal processing blocks and validate ASIC architecture for next-generation optical data-center connectivity products. The role spans algorithm development, RTL implementation support, and pre- and post-silicon system validation for high-speed SerDes and serial-link interfaces.

Experience Level

Senior-level. The posting requests candidates with advanced degrees and significant experience (MS +10 years or PhD +7 years) in DSP design for SerDes and high-speed data-center networking.

Responsibilities

Core responsibilities focus on DSP design for high-speed links and validating mixed-signal ASIC behavior across design and silicon stages.

• Design DSP blocks and evaluate architecture trade-offs for optical/electrical interconnects (PAM4, NRZ) targeting performance, power, and cost goals.
• Develop and run pre-silicon and post-silicon validation plans for digital and mixed-signal IP.
• Translate CDR and equalization architectures into synthesizable Verilog/SystemVerilog and support logic synthesis.
• Build and use MATLAB/Simulink models and behavioral models to validate algorithms and system performance.
• Execute SDF-annotated simulations, participate in static timing analysis, CDC checks, and synthesis sign-off.
• Collaborate with analog, DFT, physical design, and firmware teams to close system-level requirements.
• Document validation results and present technical findings to engineering and management stakeholders.

Requirements

Must-have technical skills and experience for the role are listed first; desirable qualifications follow.

• Extensive experience in post-silicon validation of digital and analog mixed-signal IP.
• Deep understanding of ADCs and optical/electrical interconnect architectures (100G/200G/400G per lane PAM4 and NRZ) and related design trade-offs.
• Experience translating CDR and equalization architectures into Verilog/SystemVerilog suitable for synthesis.
• Proficiency with MATLAB and Simulink; strong Verilog-HDL/SystemVerilog coding skills.
• Familiarity with front-end simulation and lint tools such as NCVerilog, NCSIM, Simvision, and Spyglass.
• Knowledge of Design for Test concepts and ability to write DFT-friendly RTL.
• Experience with synthesis flows, CDC analysis, and static timing analysis.
• Experience with SDF-annotated simulations and understanding of parasitic delays.

Nice-to-have:

• Experience with high-speed DSP algorithms (FFE, DFE, CDR adaptation) for PAM4 signals.
• Understanding of low-power logic optimization, timing margin strategies, and DFT implications.
• Knowledge of signal integrity and power integrity modeling for high-speed designs.
• Exposure to Verilog-AMS simulation and behavioral analog modeling.
• Strong written and verbal communication skills and ability to work in multifunctional teams.

Education Requirements

MS in Electrical Engineering or Computer Engineering with 10+ years of relevant DSP/SerDes experience, or PhD with 7+ years of relevant experience in digital signal processing for SerDes and high-speed serial link data-center networking. Fields explicitly mentioned: Electrical Engineering, Computer Engineering.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.