Digital Sign-off Engineer

Job Title

Digital Sign-off Engineer

Role Summary

The Sign-off Engineer owns final physical and electrical verification for completed layouts and makes the tape-out gating decision. You will run parasitic extraction, post-layout STA, DRC/LVS/ERC, power-integrity and electromigration analyses, and produce the sign-off evidence package.

This is a hands-on engineering role on the Physical Implementation team, working directly with implementation, RTL, physics and fab teams to establish and maintain sign-off methodology, checklists, and waiver discipline.

Experience Level

Mid-level (Level - Mid-Career). Candidates are expected to have production sign-off experience; the posting ranges from entry L2 (<3 years) through senior bands, but the primary requirement is demonstrated track record closing tape-outs as the sign-off engineer of record.

Responsibilities

Core responsibilities include final verification, sign-off decision-making, and method development:

• Own final verification and sign-off for layouts: parasitic extraction, post-layout STA across corners, DRC, LVS, ERC, antenna checks, and the sign-off checklist.
• Set up and run parasitic extraction and post-layout STA; develop STA constraints (SDC) from scratch when needed and interpret timing reports for implementation teams.
• Execute and close DRC/LVS/ERC/antenna checks against foundry rule decks and manage DRC waiver decisions and documentation.
• Perform power-integrity analysis: IR drop and electromigration assessments and translate findings into ECO or waiver actions.
• Produce and defend the sign-off evidence package and communicate sign-off status and risks to architects, RTL, implementation, and physics teams.
• Author and maintain sign-off methodology, scripts, constraint files, and checklists that become the organization standard.
• Partner with implementation on ECO planning and late-cycle fixes when sign-off findings require changes.

Requirements

Must-have skills and experience are listed first, followed by desirable qualifications.

• Must-have: Production-level sign-off experience with EDA tools such as Calibre, Pegasus, StarRC, PrimeTime, Voltus, or equivalents on chips that taped out and ran.
• Must-have: Demonstrated track record closing tape-outs as the sign-off engineer of record, not as an adjacent contributor.
• Must-have: Strong post-layout STA skills (multi-mode multi-corner, constraint development, and violation judgment).
• Must-have: Working fluency with foundry rule decks and disciplined DRC waiver practice, including documentation and risk assessment.
• Must-have: Solid knowledge of power integrity, IR drop, and electromigration sign-off and how implementation choices affect sign-off outcomes.
• Must-have: Methodical, detail-oriented approach appropriate for sign-off responsibilities.
• Nice-to-have: Sign-off experience on full-custom or semi-custom chips where standard flows were extended or re-derived.
• Nice-to-have: Experience with non-CMOS or research-grade PDKs (e.g., NbTiN, NbN) and building methodology where rule decks are immature.
• Nice-to-have: Custom cell modeling experience (Nanotime or equivalent) and liberty/model development for non-foundry cells.
• Nice-to-have: Track record building sign-off flows and STA environments from scratch, and late-stage ECO planning/implementation experience.
• Nice-to-have: Familiarity with superconducting digital logic (PCL, SFQ, AQFP, RSFQ) is advantageous but not required.

Education Requirements

Not specified.

About the Company

Company: Snowcap Compute

Headquarters: San Francisco, CA, United States

Snowcap Compute develops commercial superconducting digital computers using Josephson junction–based PCL logic that operate at cryogenic temperatures, aiming for dramatically lower power than CMOS. The company combines expertise in quantum physics, cryogenic engineering, and semiconductor manufacturing to build production superconducting chips.