Digital Physical Implementation and Integration Engineer

Job Title

Digital Physical Implementation and Integration Engineer

Role Summary

Owner of physical implementation and top-level integration for large digital designs in NAND memory products. Drive block and full-chip partitions through synthesis handoff, floorplan, place-and-route, timing/DRC/LVS closure, and top-level assembly.

This role collaborates with cross-functional teams (Product Engineering, Test, Probe, Process Integration, Assembly, Marketing, CAD/STA/DFT) to ensure manufacturability, performance, and timely tape-outs.

Experience Level

Mid-level. Typical candidate: 5+ years of digital physical design experience with at least one full tapeout owned end-to-end.

Responsibilities

Primary responsibilities include top-level planning, block APR, verification, automation, and cross-team coordination to deliver manufacturable silicon on schedule.

• Perform top-level design planning: virtual flat placement, global routing, partition creation, pin optimization, repeater/feedthrough planning, and power-domain planning.
• Execute top-level assembly: integrate LEF/DEF/GDS/ETM/ILM, close timing/DRC/LVS/EM/IR, and drive ECO iterations to sign-off.
• Implement block-level APR flow (floorplan → place → CTS → route → ECO → sign-off) and own block-level STA sign-off across corners.
• Generate and hand off block constraints (timing budgets, boundary SDC, ILM/ETM models, physical constraints) derived from top-level planning.
• Debug synthesis vs APR vs STA correlation and resolve PPA regressions and implementation issues.
• Perform parasitic modeling, verification with industry simulators, and support reticle experiments and tape-out revisions.
• Automate flows and tools in Tcl/Python/SKILL and contribute to shared analysis tooling and dashboards.
• Collaborate with STA, DFT, CAD, custom-layout, Test, Probe, Process Integration and Product Engineering teams; provide mentorship and document methodology.

Requirements

Must-have technical skills and experience for immediate contribution.

• 5+ years of digital physical design experience; proven end-to-end tapeout ownership.
• Strong static timing analysis and debug skills; fluent with PrimeTime across MMMC and OCV/AOCV/POCV; experience with ILM/ETM abstractions and ECO fixing.
• Hands-on expertise with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning (virtual flat, partitioning, pin optimization, budgeting, assembly).
• Proven top-level digital integration experience driving full-chip or large-partition designs from planning through assembly.
• Flat APR expertise with Innovus or ICC2: floorplan, place, CTS, route, ECO, and sign-off correlation.
• Synthesis proficiency with Design Compiler or Genus; familiarity with size_only, don't_touch, MBFF, scan, and clock gating.
• Physical verification experience with Calibre: DRC, LVS, antenna, PERC; hierarchical vs flat runs and waiver management.
• SDC authoring for multi-mode/multi-corner designs and ability to derive/validate block budgets from top-level planning.
• Fluent in Tcl and one of Python or Perl for flow automation; experience with Make-based flows, Linux/Unix, and Git or similar VCS.
• Working proficiency with general-purpose engineering AI tools and ability to use/extend internal AI toolkits from day one.
• Solid understanding of CMOS logic, standard cells, RC extraction, EM/IR, and low-power techniques (multi-voltage, power gating, retention).

Nice-to-have:

• Multi-partition SoC or memory top-level integration experience and driving ECOs across hierarchies of 5+ blocks.
• Top-level clock planning experience, memory (NAND/DRAM) or mixed-signal familiarity, and DFT/scan compression exposure.
• Familiarity with EDA vendor AI tools (Cadence Cerebrus, Synopsys DSO.ai, etc.) and contributions to methodology or CAD tooling.

Education Requirements

Bachelor's degree in Computer Engineering or Electrical Engineering required. Master's degree or Ph.D. in Computer Engineering or Electrical Engineering is preferred.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.