Digital Microarchitect

Job Title

Digital Microarchitect

Role Summary

Translate top-level chip architecture into detailed microarchitecture specifications the RTL team can implement: pipelines, datapaths, control logic, timing budgets, and the handoff artifacts between architecture and implementation.

This role sits on the Chip Architecture team and works directly with the Digital Architect, RTL designers, verification engineers, physical design, and physics teams to produce implementable, verifiable microarchitecture documents.

Experience Level

Mid-level / experienced microarchitect. Production silicon track record is expected; no explicit years-of-experience listed.

Responsibilities

Primary responsibilities include drafting and defending microarchitecture that can be implemented and verified.

• Translate architecture specifications into detailed microarchitecture documents suitable for RTL implementation.
• Define pipeline stages, datapath structures, control logic, and timing budgets for each block, including differences from CMOS assumptions.
• Own the microarchitecture-to-RTL handoff: defend specs in review, answer implementation questions, and revise specs based on implementation feedback.
• Partner with the Digital Architect to escalate micro-level issues to the architecture level when necessary.
• Collaborate directly with RTL designers and verification engineers to ensure intent is preserved in implementation and testbenches.
• Optionally own or co-own design verification for specified blocks: unit tests, architectural validation code, and checks proving implementation matches intent.
• Establish and document standards for microarchitecture artifacts at the company.

Requirements

Must-have qualifications and practical skills.

• Proven track record of microarchitecture definition on production silicon (chips that taped out and ran their intended workload).
• Ability to write clear, unambiguous microarchitecture specifications that RTL engineers can implement without repeated clarification.
• Working knowledge of the full RTL-to-GDS flow (synthesis, place & route, STA, back-end realities) and judgment to design microarchitecture that survives downstream implementation.
• Fluency operating at both architecture and RTL/implementation abstractions and ability to communicate across those levels routinely.
• Comfort writing unit tests and architectural validation code alongside spec documents.
• Comfort working in a startup environment with ambiguity and early-stage design work.

Education Requirements

Not specified.

Nice-to-have

Desirable experience that will strengthen an application.

• Microarchitecture work at major silicon companies (Apple, Qualcomm, NVIDIA, AMD) or equivalent shipped-silicon experience in senior bands.
• Experience on non-standard compute fabrics (dataflow, near-/in-memory compute, custom ISAs, AI accelerator pipelines).
• Background spanning architecture through design verification (spec, adjacent RTL, and validation).
• Experience with asynchronous, wave-pipelined, or other non-conventional clocking schemes.
• Familiarity with superconducting digital logic (PCL, SFQ, AQFP, RSFQ) is a plus.
• Track record of mentoring RTL and verification engineers; patents, publications, or visible specifications.

Working Location

This is an on-site role based at Snowcap Compute locations in the San Francisco Bay Area or Jacksonville Metro, FL.

Compensation & Benefits

Base salary range is posted in USD and varies by location; full medical, dental, vision, 401(k), and relocation assistance may be provided. Exact offer depends on experience, skills, and location.

Equal Opportunity

Snowcap Compute is an equal opportunity employer.

About the Company

Company: Snowcap Compute

Headquarters: San Francisco, CA, United States

Snowcap Compute develops commercial superconducting digital computers using Josephson junction–based PCL logic that operate at cryogenic temperatures, aiming for dramatically lower power than CMOS. The company combines expertise in quantum physics, cryogenic engineering, and semiconductor manufacturing to build production superconducting chips.