Digital IC Design Engineer - Early Career
Entry-level digital ASIC/SoC design engineer on the Data Center Engineering team. Work on block micro-architecture, RTL development, synthesis, timing closure and chip validation for high-performance, timing-critical processors used in cloud, networking and security products.
Collaborate with architects, verification, physical design, and bring-up teams to deliver optimized low-power, high-performance designs.
Entry-level (1–3 years of professional experience). Master's degree or PhD also considered. Candidates currently enrolled must graduate by December 2026.
Primary duties include block-level design and implementation through bring-up.
Must-have technical skills and professional attributes.
Bachelors degree in Computer Science, Electrical Engineering or a related field with 13 years of related professional experience, or a Masters degree and/or PhD in Computer Science, Electrical Engineering or related fields. If currently enrolled, candidates must graduate no later than December 2026. Equivalent practical experience may be considered.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
