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Digital Design Verification Staff Engineer

Synopsys
October 7, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Verification Jobs, Level - Senior

Job Title

Digital Design Verification Staff Engineer

Role Summary

Lead the design and delivery of scalable verification flows and infrastructure for Synopsys digital IP and SoC projects. Work within the Digital IP Verification Methodology (COE) team to define standards, build reusable flows, and collaborate with EDA product teams and global verification groups.

Experience Level

Senior-level. The posting describes senior expectations and technical leadership; it lists 4+ years of hands-on verification experience while the role narrative targets engineers with extensive verification leadership (including candidates with 10+ years).

Responsibilities

Design, build, and propagate verification methodologies and infrastructure that scale across IP and SoC projects.

  • Implement unified verification flows using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
  • Architect and deploy scalable verification environments for complex IP and SoC projects across global teams.
  • Define, document, and drive verification best practices and methodology standards.
  • Lead and mentor verification engineers on UVM, SystemVerilog, flow optimization, and debugging.
  • Own technical initiatives end-to-end, from concept through deployment and adoption.
  • Collaborate with EDA tool development teams to influence product roadmaps and optimize real-world workflows.
  • Troubleshoot verification flow bottlenecks and deliver durable solutions for internal teams and customers.

Requirements

Must-have technical skills and demonstrated experience for immediate contribution.

  • 4+ years of hands-on IP or SoC verification experience with proven leadership on complex verification environments.
  • Deep practical experience with Synopsys verification tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IPs (VIP).
  • Strong programming and scripting skills: SystemVerilog, UVM, Tcl, and Python for automation and flow development.
  • Proven ability to architect verification flows and infrastructure from concept to production deployment.
  • Experience managing multiple technical projects independently and communicating methodologies across global teams.
  • Ability to mentor engineers and provide clear technical documentation and guidance.
  • Nice-to-have: prior experience influencing EDA tool development or driving tool adoption in a large organization.
  • Nice-to-have: advanced degree (see Education Requirements).

Education Requirements

Bachelor's degree in Electronics, Electrical, or Computer Engineering is requested; advanced degrees (Master's/PhD) are a plus. The posting does not state an alternative "equivalent experience" clause beyond the experience requirements above.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-10-04