Digital Design Verification Principal Engineer

Job Title

Digital Design Verification Principal Engineer

Role Summary

Lead verification methodology and infrastructure development for Synopsys digital IP and SoC verification. The role sits on the Digital IP Verification Methodology (COE) team and focuses on building unified, scalable verification flows, integrating EDA tools, and accelerating verification using agentic AI techniques.

Deliver high-impact technical solutions, mentor engineers, and collaborate with global engineering and tool teams to standardize practices and improve verification efficiency.

Experience Level

Senior - typically 12+ years of hands-on IP/SoC verification experience (senior/principal engineering level).

Responsibilities

Key responsibilities include designing and delivering verification methodology, infrastructure, and automation for digital IP and SoC products.

• Apply agentic AI techniques to accelerate verification: generate verification plans, testcases, coverage analysis, and debug collateral.
• Implement reference and unified verification flows using Synopsys tools (VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs).
• Design and build robust, scalable verification infrastructures for complex IP and SoC projects.
• Define, document, and propagate verification methodologies and standards across global teams.
• Lead, mentor, and grow junior engineers; promote knowledge sharing and best practices.
• Drive technical initiatives and manage high-impact assignments to completion.
• Collaborate with tool development teams to influence product evolution and optimize verification workflows.
• Support customers and internal stakeholders by troubleshooting and refining verification processes and flows.

Requirements

Must-have technical skills and experience; nice-to-have items listed where applicable.

• Must-have: Minimum 12+ years hands-on IP/SoC verification experience with demonstrable technical contributions.
• Must-have: Strong programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar).
• Must-have: Familiarity with Synopsys verification tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Must-have: Proven ability to validate verification flows and infrastructure for complex digital designs.
• Must-have: Strong documentation, communication, and independent technical project management skills.
• Must-have: Experience leading and mentoring engineering teams.
• Nice-to-have: Exposure to agentic AI EDA tools and experience specifically with Cursor and/or VS Code co-pilot.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or Computer Engineering (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.