Digital Design Engineer Intern - Fall 2026
Marvell TechnologyJob Title
Digital Design Engineer Intern - Fall 2026
Role Summary
Internship on the Central Engineering team within Custom Compute Solutions (CCSBU). Work supports digital IC design for high-performance architectures in areas such as AI, data movement, storage, networking and security.
The role involves RTL development, circuit analysis across PVT conditions, and collaboration with architects, designers, verification, and physical design engineers toward milestone-driven ASIC projects.
Experience Level
Entry-level intern. Intended for current university students enrolled in an undergraduate or masters program (see Education Requirements).
Responsibilities
Typical tasks during the internship include hands-on design, analysis, and cross-functional collaboration.
- Perform circuit and block-level analysis across Process, Voltage, and Temperature (PVT) to verify performance, power, and area targets.
- Analyze, debug, refine, and validate designs under mentor guidance; document and summarize results for cross-functional teams.
- Design and develop RTL modules for logical blocks and functional units within high-performance architectures.
- Help define block-level requirements to meet power, performance, and area targets for next-generation products.
- Work on ASIC design flow aspects: RTL lint, block-level assertions, synthesis timing constraints, and timing closure.
- Collaborate with architects, designers, verification, and physical design engineers to resolve technical issues.
Requirements
Must-have technical skills, work setting, and communication expectations; listed concisely.
- Working knowledge of Verilog or SystemVerilog.
- Familiarity with digital electronics fundamentals.
- Strong written and verbal communication; able to work collaboratively and independently.
- Full-time, on-site work required.
Nice-to-have:
- Experience with Cadence Virtuoso, Spectre X, or similar circuit analysis tools.
- Experience with Python or Perl scripting and Linux-based data analysis workflows.
- Familiarity with synthesis, timing constraints, and timing closure practices.
Education Requirements
Must be currently enrolled in a university program working toward a BS or MS degree in Computer Engineering, Electrical Engineering, or an equivalent technical degree.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
