Digital Design Engineer, DMTS/SMTS/MTS

Job Title

Digital Design Engineer, DMTS/SMTS/MTS

Role Summary

Responsible for front-end RTL design and microarchitecture for complex DRAM, memory, and mixed-signal digital blocks. Delivers RTL from architecture and specification through synthesis, timing closure, and implementation handoff.

Works closely with architecture, verification, circuit design, and physical implementation teams to meet performance, power, area, and quality targets and to improve design methodologies.

Experience Level

Senior-level. Target experience: 10+ years in ASIC/SoC front-end design; 12–15+ years preferred for principal or technical-lead roles.

Responsibilities

Primary responsibilities include delivering front-end RTL and ensuring successful integration and handoff.

• Design, develop, and deliver high-quality RTL for DRAM, memory, and mixed-signal digital blocks.
• Own front-end ASIC design activities: RTL development, linting, CDC/RDC verification, and functional validation.
• Drive synthesis, static timing analysis (STA), timing constraint definition, and timing closure across multi-mode, multi-corner conditions.
• Develop and maintain design constraints (SDC), clock definitions, timing exceptions, I/O constraints, and UPF-based power intent.
• Analyze synthesis and timing reports to identify critical bottlenecks and implement improvements to meet PPA and schedule targets.
• Collaborate with architecture, verification, circuit, and physical implementation teams to resolve integration challenges.
• Contribute to design methodology, automation frameworks, and RTL-to-GDS implementation flows.
• Mentor peers and promote continuous improvement, including automation and AI-assisted engineering tools.

Requirements

Must-have technical skills and experience for the role.

• 10+ years of relevant ASIC or SoC front-end design experience with significant ownership of complex projects.
• Advanced proficiency in RTL design and microarchitecture development using Verilog and SystemVerilog.
• Proven ability to take designs from architecture and specification through RTL implementation, verification support, synthesis, timing closure, and handoff.
• Experience with synthesis, STA, timing constraints, CDC/RDC verification, linting, and functional validation.
• Experience developing and optimizing SDC and UPF-based power intent and low-power implementation methodologies.
• Familiarity with industry-standard EDA tools and CMOS digital/mixed-signal concepts.
• Strong problem-solving, communication, and collaboration skills; experience mentoring engineers.
• Nice-to-have: prior work on DRAM/memory IP, experience driving automation or generative AI-assisted engineering workflows, and 12–15+ years for principal/lead roles.

Education Requirements

Bachelor's or Master's degree (or equivalent practical experience) in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.