Digital Design Engineer, Air Dominance and Strike

Job Title

Digital Design Engineer, Air Dominance and Strike

Role Summary

Member of the Air Dominance and Strike (AD&S) Electrical Engineering team delivering avionics, embedded processing, and FPGA-based systems for Group 5 air vehicles and missile platforms. Responsible for designing, implementing, and integrating RTL for FPGA/SoC platforms used in high-performance, mission-critical embedded systems.

Experience Level

Entry-level (2+ years of relevant FPGA, ASIC, or digital design experience)

Responsibilities

Design, implement, verify, and integrate FPGA/SoC functionality across the full development cycle.

• Write RTL in VHDL, Verilog, or SystemVerilog and develop microarchitecture and interface definitions.
• Deliver FPGA designs or major functional blocks from architecture through timing closure and lab debug.
• Create and run simulation, synthesis, and implementation flows; achieve timing and resource closure.
• Debug functional, timing, and integration issues in simulation and on hardware; support board bring-up and lab validation.
• Collaborate with hardware, embedded software, systems, and verification engineers for system integration.
• Participate in design reviews, code reviews, and produce technical documentation and reusable IP/design practices.

Requirements

Must-have technical skills and constraints; preferred items listed separately.

• Must-have: Minimum 2 years of FPGA, ASIC, or closely related digital design experience.
• Must-have: Proficiency in VHDL and/or Verilog/SystemVerilog.
• Must-have: Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
• Must-have: Practical debug experience in simulation and on hardware; strong digital design fundamentals (clocking, resets, state machines, CDC, interface design).
• Must-have: Comfortable in Linux-based development environments, Git workflows, and Tcl and/or Python scripting.
• Must-have: Strong written and verbal communication skills and eligibility to obtain and maintain a U.S. Secret security clearance.
• Nice-to-have: Experience owning a major FPGA subsystem, familiarity with AMD (Xilinx), Intel/Altera, or Lattice toolchains, and knowledge of high-speed/embedded interfaces (Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, MIL-STD-1553).
• Nice-to-have: Familiarity with DO-254 or safety-critical standards, embedded hardware/software co-design (e.g., Vitis), and experience with verification infrastructure, CI/CD, and reproducible build environments.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated). No alternative degree-or-experience equivalency was specified in the posting.

About the Company

Company: Anduril

Headquarters: Costa Mesa, CA, USA

Anduril is a defense technology company that builds autonomous systems, AI, sensor-fusion, and computer-vision-enabled platforms for U.S. and allied military and intelligence customers, powered by its Lattice OS to accelerate delivery of operational capabilities.